diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-10-21 18:22:32 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2014-11-20 19:03:26 +0100 |
| commit | e8b4da2f6f8b6fc38db82b1a2e1b9b9340ecfc53 (patch) | |
| tree | cd666b7de5e9509ee8d20627dc7cb3f961426476 /src/mainboard/amd/olivehillplus/devicetree.cb | |
| parent | e4c17ce8036ae247f5e73c37789a9181e7cbd3c7 (diff) | |
AMD: Isolate AGESA and PI build environments for southbridge
To backport features introduced with recent Chromebooks and/or Intel
boards in general, heavy work on the AMD AGESA platform infrastructure
is required. With the AGESA PI available in binary form only, community
members have little means to verify, debug and develop for the said
platforms.
Thus it makes sense to fork the existing agesawrapper interfaces, to give
AMD PI platforms a clean and independent sandbox. New directory layout
reflects the separation already taken place under 3rdparty/ and vendorcode/.
Change-Id: Ia730f0e45e7c1bdfc0c91e95eb6729a77773e2b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7388
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/amd/olivehillplus/devicetree.cb')
| -rw-r--r-- | src/mainboard/amd/olivehillplus/devicetree.cb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/amd/olivehillplus/devicetree.cb b/src/mainboard/amd/olivehillplus/devicetree.cb index aec71f9d72..3c5e38f4cd 100644 --- a/src/mainboard/amd/olivehillplus/devicetree.cb +++ b/src/mainboard/amd/olivehillplus/devicetree.cb @@ -39,7 +39,7 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 2.5 on end # Edge Connector end #chip northbridge/amd/pi/00730F01 - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + chip southbridge/amd/pi/avalon # it is under NB/SB Link, but on the same pci bus device pci 10.0 on end # XHCI HC0 device pci 11.0 on end # SATA device pci 12.0 on end # USB @@ -57,7 +57,7 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 14.2 on end # HDA 0x4383 device pci 14.3 on end # LPC 0x439d device pci 14.7 on end # SD - end #chip southbridge/amd/hudson + end #chip southbridge/amd/pi/avalon device pci 18.0 on end device pci 18.1 on end |