diff options
| author | Bruce Griffith <Bruce.Griffith@se-eng.com> | 2014-12-08 01:43:23 -0700 |
|---|---|---|
| committer | Bruce Griffith <Bruce.Griffith@se-eng.com> | 2014-12-10 19:33:46 +0100 |
| commit | 87543425d7734099aed6c1def595ee4d710d6ce0 (patch) | |
| tree | 3e506cfbfd7df8a1a72226eeb70eee1f3c45bdba /src/mainboard/amd/olivehillplus/devicetree.cb | |
| parent | e420139a525bd964a4be8dd82d7254c631fed669 (diff) | |
AMD 00730F01: Topology changes required by KaveriPI v1.1.0.7 update
The updated KaveriPI binary, upgrading to v1.1.0.7, requires changes
to define the PSP device (PCI 0:08.0) and the IOMMU device (PCI 0:00.2).
In the new AGESA binary, the IOMMU device is enabled and must be
disabled in devicetree.cb and agesawrapper_amdinitenv() to maintain
the same level of functionality.
Change-Id: I3f47e0bd5a75729ec1e4b7b11885d0622c474342
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/7727
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/amd/olivehillplus/devicetree.cb')
| -rw-r--r-- | src/mainboard/amd/olivehillplus/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/amd/olivehillplus/devicetree.cb b/src/mainboard/amd/olivehillplus/devicetree.cb index 3c5e38f4cd..65f7ee4577 100644 --- a/src/mainboard/amd/olivehillplus/devicetree.cb +++ b/src/mainboard/amd/olivehillplus/devicetree.cb @@ -29,6 +29,7 @@ chip northbridge/amd/pi/00730F01/root_complex chip northbridge/amd/pi/00730F01 # PCI side of HT root complex device pci 0.0 on end # Root Complex + device pci 0.2 off end # IOMMU device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 device pci 1.1 on end # Internal Multimedia device pci 2.0 on end # PCIe Host Bridge @@ -37,6 +38,7 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 2.3 on end # Realtek NIC device pci 2.4 on end # Edge Connector device pci 2.5 on end # Edge Connector + device pci 8.0 on end # Platform Security Processor end #chip northbridge/amd/pi/00730F01 chip southbridge/amd/pi/avalon # it is under NB/SB Link, but on the same pci bus @@ -57,6 +59,7 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 14.2 on end # HDA 0x4383 device pci 14.3 on end # LPC 0x439d device pci 14.7 on end # SD + device pci 16.0 on end # USB end #chip southbridge/amd/pi/avalon device pci 18.0 on end |