diff options
| author | Anand Vaikar <a.vaikar2021@gmail.com> | 2023-03-29 12:46:33 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-08-23 16:09:00 +0000 |
| commit | 1855cb46440dea33eed93e32bb93dad137c6170b (patch) | |
| tree | fcb236c6f5e5c8302b60c35a598787c9e4e4ecf0 /src/mainboard/amd/mayan/ec.c | |
| parent | 40c740584bd86a535924c0b0337f9ef094f3d394 (diff) | |
mb/amd/mayan: Enable the DT and M.2 SSD1 PCIE slots
Program the EC GPIOs to enable the DT or M.2 SSD1
PCIe slots based on the config option selected.
Change-Id: Id141e5e55ef6e25722b411975a59c9764b86f624
Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Diffstat (limited to 'src/mainboard/amd/mayan/ec.c')
| -rw-r--r-- | src/mainboard/amd/mayan/ec.c | 39 |
1 files changed, 36 insertions, 3 deletions
diff --git a/src/mainboard/amd/mayan/ec.c b/src/mainboard/amd/mayan/ec.c index d60814fe9a..07d71de69a 100644 --- a/src/mainboard/amd/mayan/ec.c +++ b/src/mainboard/amd/mayan/ec.c @@ -17,6 +17,7 @@ #define EC_GPIO_3_ADDR 0xA3 #define EC_GPIO_EVAL_RST_AUX BIT(0) #define EC_GPIO_LOM_RESET_AUX BIT(1) +#define EC_GPIO_DT_RESET_AUX BIT(2) #define EC_GPIO_7_ADDR 0xA7 #define EC_GPIO_DT_PWREN BIT(2) @@ -25,6 +26,9 @@ #define EC_GPIO_8_ADDR 0xA8 #define EC_GPIO_SMBUS0_EN BIT(0) +#define EC_GPIO_9_ADDR 0xA9 +#define EC_GPIO_M2SSD1_PWREN BIT(5) + #define EC_GPIO_A_ADDR 0xAA #define EC_GPIO_WWAN_PWREN BIT(3) #define EC_GPIO_M2_SSD0_PWREN BIT(6) @@ -34,6 +38,7 @@ #define EC_GPIO_DT_N_WLAN_SW BIT(1) #define EC_GPIO_MP2_SEL BIT(2) #define EC_GPIO_WWAN_N_LOM_SW BIT(3) +#define EC_GPIO_M2SSD1_HDD_SW BIT(6) #define EC_SW02_ADDR 0xB7 #define EC_SW02_MS BIT(7) @@ -42,8 +47,7 @@ static void configure_ec_gpio(void) { uint8_t tmp; - /* Enable MXM slot: set EC_GPIO_EVAL_PWREN, EC_GPIO_EVAL_SLOT_PWR - and EC_GPIO_EVAL_RST_AUX */ + /* Enable MXM slot */ tmp = ec_read(EC_GPIO_1_ADDR); tmp |= EC_GPIO_EVAL_PWREN; ec_write(EC_GPIO_1_ADDR, tmp); @@ -54,22 +58,51 @@ static void configure_ec_gpio(void) tmp = ec_read(EC_GPIO_3_ADDR); tmp |= EC_GPIO_LOM_RESET_AUX | EC_GPIO_EVAL_RST_AUX; + tmp |= EC_GPIO_LOM_RESET_AUX; + /* Enable DT slot */ + if (CONFIG(ENABLE_DT_SLOT_MAYAN)) + tmp |= EC_GPIO_DT_RESET_AUX; + else + tmp &= (~EC_GPIO_DT_RESET_AUX); + ec_write(EC_GPIO_3_ADDR, tmp); tmp = ec_read(EC_GPIO_7_ADDR); - tmp |= EC_GPIO_WWAN_MODULE_RST | EC_GPIO_DT_PWREN; + tmp |= EC_GPIO_WWAN_MODULE_RST; + if (CONFIG(ENABLE_DT_SLOT_MAYAN)) + tmp |= EC_GPIO_DT_PWREN; + else + tmp &= (~EC_GPIO_DT_PWREN); + ec_write(EC_GPIO_7_ADDR, tmp); tmp = ec_read(EC_GPIO_8_ADDR); tmp |= EC_GPIO_SMBUS0_EN; ec_write(EC_GPIO_8_ADDR, tmp); + tmp = ec_read(EC_GPIO_9_ADDR); + /* Enable M2 SSD1 slot */ + if (CONFIG(ENABLE_M2_SSD1_MAYAN)) + tmp |= EC_GPIO_M2SSD1_PWREN; + else + tmp &= (~EC_GPIO_M2SSD1_PWREN); + + ec_write(EC_GPIO_9_ADDR, tmp); + tmp = ec_read(EC_GPIO_A_ADDR); tmp |= EC_GPIO_M2_SSD0_PWREN | EC_GPIO_LOM_PWREN | EC_GPIO_WWAN_PWREN; ec_write(EC_GPIO_A_ADDR, tmp); tmp = ec_read(EC_GPIO_C_ADDR); tmp |= EC_GPIO_WWAN_N_LOM_SW | EC_GPIO_MP2_SEL | EC_GPIO_DT_N_WLAN_SW; + if (CONFIG(ENABLE_DT_SLOT_MAYAN)) { + tmp |= EC_GPIO_M2SSD1_HDD_SW; + tmp &= (~EC_GPIO_DT_N_WLAN_SW); + } + if (CONFIG(ENABLE_M2_SSD1_MAYAN)) { + tmp |= EC_GPIO_DT_N_WLAN_SW; + tmp &= (~EC_GPIO_M2SSD1_HDD_SW); + } ec_write(EC_GPIO_C_ADDR, tmp); tmp = ec_read(EC_SW02_ADDR); |