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authorJohn Zhao <john.zhao@intel.com>2021-02-16 09:22:47 -0800
committerTim Wawrzynczak <twawrzynczak@chromium.org>2021-02-23 22:14:04 +0000
commit2c7842407af8e84b28d41e8369ccf199748f65ce (patch)
tree304d4206cb923aba3e058bc32bf30e75e8676876 /src/mainboard/amd/mandolin
parent83e6c15b0ea252d5475c3a5af25279765e19aa4d (diff)
soc/intel/tigerlake: Remove polling for Link Active Status at resume
Tigerlake TBT only has SW CM support. The polling for "LA == 1" is not applicable for SW CM platform at the resume sequence. This change removes the pollng for "LA == 1" to improve resume performance. BUG=b:177519081 TEST=Boot to kernel and validated s0ix on Voxel board. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I886001f71bf893dc7eda98403fa4e1a3de6b958e Reviewed-on: https://review.coreboot.org/c/coreboot/+/50806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/amd/mandolin')
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