diff options
| author | Felix Held <felix.held@amd.corp-partner.google.com> | 2020-04-04 05:27:05 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-21 01:17:31 +0000 |
| commit | e6315f74d6f402734e476a57a8faf4ac9cb23d38 (patch) | |
| tree | 21ef786a292ad9ec95bbbb196d9234588d6ffa97 /src/mainboard/amd/mandolin/dsdt.asl | |
| parent | 12b0f7746e6ce8c3eeb677e093b756aeb8ede493 (diff) | |
mb/amd/mandolin: Add Picasso CRB
Mandolin is the CRB for AMD Picasso and Dali.
The mainboard code still needs a little cleanup and verification, but
I'll do that in a follow-up to have a non Chromebook board using the
Picasso SoC code in tree as soon as possible to be able to detect some
possible breakage.
BUG=b:130660285
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I2b4a78e1eef9f998e1986da1506201eb505822eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33772
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/mandolin/dsdt.asl')
| -rw-r--r-- | src/mainboard/amd/mandolin/dsdt.asl | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl new file mode 100644 index 0000000000..02a661918f --- /dev/null +++ b/src/mainboard/amd/mandolin/dsdt.asl @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define MAINBOARD_HAS_SPEAKER 1 + +/* DefinitionBlock Statement */ +#include <acpi/acpi.h> +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* as needed */ + + /* global NVS and variables */ + #include <globalnvs.asl> + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include <pcie.asl> + + /* Describe the processor tree (\_PR) */ + #include <cpu.asl> + + /* Contains the supported sleep states for this chipset */ + #include <sleepstates.asl> + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* Contains _SWS methods */ + #include <soc/amd/common/acpi/acpi_wake_source.asl> + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include <arch/x86/acpi/globutil.asl> + + /* Describe the SOC */ + #include <soc.asl> + + } /* End \_SB scope */ + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" +} +/* End of ASL file */ |