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authorRichard Spiegel <richard.spiegel@amd.corp-partner.google.com>2018-04-18 08:06:33 -0700
committerPatrick Georgi <pgeorgi@google.com>2018-04-20 13:03:14 +0000
commit6fcb9b00c8b7f820bb5ef81a83a24cd656654272 (patch)
tree3cb9214d55eed3311fd071af4ca32739ba567df9 /src/mainboard/amd/gardenia
parente6db1895617a50eabf9f1a0b40025e8a74817cc3 (diff)
soc/amd/stoneyridge/include/soc/southbridge.c: Rename gpio structure
The GPIO definition structure has evolved to a point where it's no longer specific to stoneyridge, though probably still specific to AMD. Therefore, rename the GPIO declaration structure removing stoneyridge from it. BUG=b:72875858 TEST=Build kahlee, grunt, gardenia. Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25726 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/gardenia')
-rw-r--r--src/mainboard/amd/gardenia/bootblock/bootblock.c2
-rw-r--r--src/mainboard/amd/gardenia/gpio.c8
-rw-r--r--src/mainboard/amd/gardenia/gpio.h4
-rw-r--r--src/mainboard/amd/gardenia/mainboard.c2
4 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/amd/gardenia/bootblock/bootblock.c b/src/mainboard/amd/gardenia/bootblock/bootblock.c
index cb2a13516b..140bc07529 100644
--- a/src/mainboard/amd/gardenia/bootblock/bootblock.c
+++ b/src/mainboard/amd/gardenia/bootblock/bootblock.c
@@ -21,7 +21,7 @@
void bootblock_mainboard_early_init(void)
{
size_t num_gpios;
- const struct soc_amd_stoneyridge_gpio *gpios;
+ const struct soc_amd_gpio *gpios;
gpios = early_gpio_table(&num_gpios);
sb_program_gpios(gpios, num_gpios);
}
diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c
index 6672ea5c21..7c5f47b25a 100644
--- a/src/mainboard/amd/gardenia/gpio.c
+++ b/src/mainboard/amd/gardenia/gpio.c
@@ -24,7 +24,7 @@
* bootblock while GPIO pins used only by the OS should be initialized at
* ramstage.
*/
-const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = {
+static const struct soc_amd_gpio gpio_set_stage_reset[] = {
/* NFC PU */
PAD_GPO(GPIO_64, HIGH),
/* PCIe presence detect */
@@ -45,7 +45,7 @@ const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = {
PAD_NF(GPIO_143, UART1_TXD, PULL_NONE),
};
-const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = {
+static const struct soc_amd_gpio gpio_set_stage_ram[] = {
/* BT radio disable */
PAD_GPO(GPIO_14, HIGH),
/* NFC wake */
@@ -56,13 +56,13 @@ const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = {
PAD_GPO(GPIO_70, HIGH),
};
-const struct soc_amd_stoneyridge_gpio *early_gpio_table(size_t *size)
+const struct soc_amd_gpio *early_gpio_table(size_t *size)
{
*size = ARRAY_SIZE(gpio_set_stage_reset);
return gpio_set_stage_reset;
}
-const struct soc_amd_stoneyridge_gpio *gpio_table(size_t *size)
+const struct soc_amd_gpio *gpio_table(size_t *size)
{
*size = ARRAY_SIZE(gpio_set_stage_ram);
return gpio_set_stage_ram;
diff --git a/src/mainboard/amd/gardenia/gpio.h b/src/mainboard/amd/gardenia/gpio.h
index f3869448f5..1d3a8a2508 100644
--- a/src/mainboard/amd/gardenia/gpio.h
+++ b/src/mainboard/amd/gardenia/gpio.h
@@ -16,7 +16,7 @@
#ifndef MAINBOARD_GPIO_H
#define MAINBOARD_GPIO_H
-const struct soc_amd_stoneyridge_gpio *early_gpio_table(size_t *size);
-const struct soc_amd_stoneyridge_gpio *gpio_table(size_t *size);
+const struct soc_amd_gpio *early_gpio_table(size_t *size);
+const struct soc_amd_gpio *gpio_table(size_t *size);
#endif /* MAINBOARD_GPIO_H */
diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c
index 71fa257318..9853803896 100644
--- a/src/mainboard/amd/gardenia/mainboard.c
+++ b/src/mainboard/amd/gardenia/mainboard.c
@@ -81,7 +81,7 @@ static void pirq_setup(void)
static void mainboard_init(void *chip_info)
{
size_t num_gpios;
- const struct soc_amd_stoneyridge_gpio *gpios;
+ const struct soc_amd_gpio *gpios;
gpios = gpio_table(&num_gpios);
sb_program_gpios(gpios, num_gpios);
}