diff options
| author | Marshall Dawson <marshalldawson3rd@gmail.com> | 2017-06-23 12:02:23 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-06-26 00:46:36 +0000 |
| commit | 7d4ba55343d7dd82945d5cdeb74e349b3c30ce2d (patch) | |
| tree | 05e5c2e7cd2de98f91f42b94194f628693e92ac3 /src/mainboard/amd/gardenia/mptable.c | |
| parent | 2df118cdf04c72156ca92b940063288968ca7cea (diff) | |
amd/gardenia: Fix most checkpatch errors
Correct all checkpatch errors but leave two errors in place
that are caused by AMD typing.
Change-Id: I9daa374da76ff991de72d16bad0e8b586aa95525
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd/gardenia/mptable.c')
| -rw-r--r-- | src/mainboard/amd/gardenia/mptable.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c index 0d9064f057..f32b8dad89 100644 --- a/src/mainboard/amd/gardenia/mptable.c +++ b/src/mainboard/amd/gardenia/mptable.c @@ -26,7 +26,7 @@ #include <soc/hudson.h> #include <amd_pci_util.h> -static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length) { mc->mpc_length += length; mc->mpc_entry_count++; @@ -75,16 +75,20 @@ static void *smp_write_config_table(void *v) smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ - smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + smp_write_lintsrc(mc, (type), \ + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, \ + (intr), (apicid), (pin)) mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); /* PCI interrupts are level triggered, and are * associated with a specific bus/device/function tuple. */ #define PCI_INT(bus, dev, int_sign, pin) \ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + smp_write_intsrc(mc, mp_INT, \ + MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), \ + (((dev)<<2)|(int_sign)), ioapic_id, (pin)) /* Internal VGA */ PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[0x02]); @@ -146,7 +150,7 @@ static void *smp_write_config_table(void *v) /* FCH PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13); - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); /* There is no extension information... */ |