soc/amd/stoneyridge: Normalize GPIO init

This makes the flow for GPIO initialization more closely follow that
what is performed for other boards so that it's easier to read the flow
(and stops relying on BS_WRITE_TABLES).

BUG=b:72875858
TEST=Built and booted grunt, built gardenia.

Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23679
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

1 files changed, 11 insertions, 1 deletions

diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c
index 824fd9d979..71fa257318 100644
--- a/src/mainboard/amd/gardenia/mainboard.c
+++ b/src/mainboard/amd/gardenia/mainboard.c
@@ -18,6 +18,9 @@
 #include <arch/acpi.h>
 #include <amdblocks/agesawrapper.h>
 #include <amdblocks/amd_pci_util.h>
+#include <soc/southbridge.h>
+
+#include "gpio.h"
 
 /***********************************************************
  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
@@ -75,7 +78,13 @@ static void pirq_setup(void)
 	picr_data_ptr = mainboard_picr_data;
 }
 
-
+static void mainboard_init(void *chip_info)
+{
+	size_t num_gpios;
+	const struct soc_amd_stoneyridge_gpio *gpios;
+	gpios = gpio_table(&num_gpios);
+	sb_program_gpios(gpios, num_gpios);
+}
 
 /*************************************************
  * enable the dedicated function in gardenia board.
@@ -90,5 +99,6 @@ static void gardenia_enable(device_t dev)
 }
 
 struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
 	.enable_dev = gardenia_enable,
 };