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authorMarc Jones <marcj303@gmail.com>2017-05-05 16:15:31 -0600
committerMartin Roth <martinroth@google.com>2017-06-26 00:46:30 +0000
commit2df118cdf04c72156ca92b940063288968ca7cea (patch)
treefe3ed54c1cc3fffc69ca07f52bfbafd2a67f5fe4 /src/mainboard/amd/gardenia/dsdt.asl
parent1587dc8a2b4ddfe110cd0239c6506a320cccac96 (diff)
amd/gardenia: Switch to soc/amd/stoneyridge
Switch Garnenia mainboard to single soc/ directory structure. Change-Id: I095804d603bcccf324d3244965081a9dccba62ae Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/19725 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/amd/gardenia/dsdt.asl')
-rw-r--r--src/mainboard/amd/gardenia/dsdt.asl16
1 files changed, 8 insertions, 8 deletions
diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl
index 0d36a60c68..2245ea2af0 100644
--- a/src/mainboard/amd/gardenia/dsdt.asl
+++ b/src/mainboard/amd/gardenia/dsdt.asl
@@ -32,20 +32,20 @@ DefinitionBlock (
#include "acpi/usb_oc.asl"
/* PCI IRQ mapping for the Southbridge */
- #include <southbridge/amd/pi/hudson/acpi/pcie.asl>
+ #include <pcie.asl>
/* Describe the processor tree (\_PR) */
- #include <cpu/amd/pi/00670F00/acpi/cpu.asl>
+ #include <cpu.asl>
/* Contains the supported sleep states for this chipset */
- #include <southbridge/amd/pi/hudson/acpi/sleepstates.asl>
+ #include <sleepstates.asl>
/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
#include "acpi/sleep.asl"
/* System Bus */
Scope(\_SB) { /* Start \_SB scope */
- /* global utility methods expected within the \_SB scope */
+ /* global utility methods expected within the \_SB scope */
#include <arch/x86/acpi/globutil.asl>
/* Describe IRQ Routing mapping for this platform (within the \_SB scope) */
@@ -60,14 +60,14 @@ DefinitionBlock (
Device(PCI0) {
/* Describe the AMD Northbridge */
- #include <northbridge/amd/pi/00670F00/acpi/northbridge.asl>
+ #include <northbridge.asl>
/* Describe the AMD Fusion Controller Hub Southbridge */
- #include <southbridge/amd/pi/hudson/acpi/fch.asl>
+ #include <fch.asl>
}
/* Describe PCI INT[A-H] for the Southbridge */
- #include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
+ #include <pci_int.asl>
/* Describe the devices in the Southbridge */
#include "acpi/carrizo_fch.asl"
@@ -75,7 +75,7 @@ DefinitionBlock (
} /* End \_SB scope */
/* Describe SMBUS for the Southbridge */
- #include <southbridge/amd/pi/hudson/acpi/smbus.asl>
+ #include <smbus.asl>
/* Define the General Purpose Events for the platform */
#include "acpi/gpe.asl"