diff options
| author | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-08-02 20:08:35 +1000 |
|---|---|---|
| committer | Edward O'Callaghan <eocallaghan@alterapraxis.com> | 2014-08-23 05:30:42 +0200 |
| commit | 47b8075bb14de4dad4cfd2c2f42482e04644b28d (patch) | |
| tree | eabeb1e0762ee83cdeec20c4b1a01baee6563141 /src/mainboard/amd/dinar | |
| parent | 8b685398a74065d832fe2a3dfcfb313f0f4f11c3 (diff) | |
superio/smsc/sio1036: Fix hardcoded TTY0 base addr and .c include
Compile romstage component as link-time symbols. Pass CONFIG_TTY0_BASE
as argument instead of hard coding and playing funny business with the
pre-processor. Fix board to match.
Change-Id: If6d0d5389bd4e7765bb6056cf488c94fd45915c2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6463
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Diffstat (limited to 'src/mainboard/amd/dinar')
| -rw-r--r-- | src/mainboard/amd/dinar/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/amd/dinar/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/amd/dinar/romstage.c | 10 |
3 files changed, 5 insertions, 8 deletions
diff --git a/src/mainboard/amd/dinar/Kconfig b/src/mainboard/amd/dinar/Kconfig index e826459968..b71c5a570e 100644 --- a/src/mainboard/amd/dinar/Kconfig +++ b/src/mainboard/amd/dinar/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_AMD_AGESA_FAMILY15 select NORTHBRIDGE_AMD_CIMX_RD890 select SOUTHBRIDGE_AMD_CIMX_SB700 + select SUPERIO_SMSC_SIO1036 select SUPERIO_SMSC_SCH4037 select BOARD_ROMSIZE_KB_2048 select HAVE_OPTION_TABLE diff --git a/src/mainboard/amd/dinar/devicetree.cb b/src/mainboard/amd/dinar/devicetree.cb index 09becd431f..7a59fd29a3 100644 --- a/src/mainboard/amd/dinar/devicetree.cb +++ b/src/mainboard/amd/dinar/devicetree.cb @@ -85,7 +85,7 @@ chip northbridge/amd/agesa/family15/root_complex irq 0x70 = 1 # PS/2 keyboard interrupt irq 0x72 = 12 # PS/2 mouse interrupt end - end #SIO SMSC307 + end #SIO SMSC SCH4037 end #LPC device pci 14.4 on end # PCI bridge, 0x4384 device pci 14.5 on end # USB 3 diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 842b4f0ec7..8cc3d9a50f 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -33,12 +33,12 @@ #include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "superio/smsc/sch4037/sch4037_early_init.c" -#include "superio/smsc/sio1036/sio1036_early_init.c" +#include <superio/smsc/sio1036/sio1036.h> #include "cpu/x86/lapic.h" #include "nb_cimx.h" #include <sb_cimx.h> -#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) +#define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1) void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -50,11 +50,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sch4037_early_init(0x2e); - /* Detect SMSC SIO1036 LPC Debug Card status */ - if (detect_sio1036_chip(0x4E)) { - /* Found SMSC SIO1036 LPC Debug Card */ - sio1036_early_init(0x4E); - } + sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); post_code(0x31); console_init(); |