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authorKyösti Mälkki <kyosti.malkki@gmail.com>2015-11-02 13:02:08 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2016-07-20 06:36:23 +0200
commitf9a5d5fa635e80382c444a02b2385014ea1ec77a (patch)
treed0ac6652d559df23f4ba54418f1a454f1f0d7ada /src/mainboard/amd/db-ft3b-lc/romstage.c
parent546eb451e31f6513ed7a2039fe5848ba04954870 (diff)
amd/db-ft3b-lc: Add board support
Change-Id: Ibab9039306730bfd3063b34cf085e854e4608902 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14970 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Diffstat (limited to 'src/mainboard/amd/db-ft3b-lc/romstage.c')
-rw-r--r--src/mainboard/amd/db-ft3b-lc/romstage.c10
1 files changed, 0 insertions, 10 deletions
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c
index a5c529e7c5..c64fe4e3bc 100644
--- a/src/mainboard/amd/db-ft3b-lc/romstage.c
+++ b/src/mainboard/amd/db-ft3b-lc/romstage.c
@@ -68,16 +68,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val);
printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx);
- /*
- * This refers to LpcClkDrvSth settling time. Without this setting, processor
- * initialization is slow or incorrect, so this wait has been replicated from
- * earlier development boards.
- */
- {
- int i;
- for(i = 0; i < 200000; i++) inb(0xCD6);
- }
-
post_code(0x37);
AGESAWRAPPER(amdinitreset);