From f9a5d5fa635e80382c444a02b2385014ea1ec77a Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Mon, 2 Nov 2015 13:02:08 +0200 Subject: amd/db-ft3b-lc: Add board support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ibab9039306730bfd3063b34cf085e854e4608902 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/14970 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Martin Roth Reviewed-by: Philipp Deppenwiese --- src/mainboard/amd/db-ft3b-lc/romstage.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'src/mainboard/amd/db-ft3b-lc/romstage.c') diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index a5c529e7c5..c64fe4e3bc 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -68,16 +68,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); - /* - * This refers to LpcClkDrvSth settling time. Without this setting, processor - * initialization is slow or incorrect, so this wait has been replicated from - * earlier development boards. - */ - { - int i; - for(i = 0; i < 200000; i++) inb(0xCD6); - } - post_code(0x37); AGESAWRAPPER(amdinitreset); -- cgit v1.2.3