diff options
author | Felix Held <felix-coreboot@felixheld.de> | 2022-01-11 16:22:35 +0100 |
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committer | Felix Held <felix-coreboot@felixheld.de> | 2022-01-25 03:19:15 +0000 |
commit | a8d7c043f67aee61280b3851e938f2c1de252f06 (patch) | |
tree | e278a155f6b2e5362c26c21533fbabe29fb5ae98 /src/mainboard/amd/chausie/Makefile.inc | |
parent | 421c7d1a9904f1f74d017c053da9cc4a4e1586aa (diff) |
mb/amd/chausie: add mainboard as copy of mb/amd/majolica
To have the new AMD Sabrina SoC code tested, add the AMD Chausie
mainboard as a copy of Majolica. This patch also changes the name from
Majolica to Chausie, selects the Sabrina SoC instead of the Cezanne SoC
and comments out the APCB_SOURCES since those aren't available in the
3rdparty/blobs repository yet.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic7b18f7a6ae5b8365234dd1227e0b1f7f37279da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/mainboard/amd/chausie/Makefile.inc')
-rw-r--r-- | src/mainboard/amd/chausie/Makefile.inc | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/src/mainboard/amd/chausie/Makefile.inc b/src/mainboard/amd/chausie/Makefile.inc new file mode 100644 index 0000000000..bb742707f9 --- /dev/null +++ b/src/mainboard/amd/chausie/Makefile.inc @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += early_gpio.c + +romstage-y += port_descriptors.c + +ramstage-y += chromeos.c + +#TODO: add APCB binaries +#APCB_SOURCES = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4.bin +#APCB_SOURCES_RECOVERY = $(MAINBOARD_BLOBS_DIR)/APCB_CZN_D4_DefaultRecovery.bin + +ifeq ($(CONFIG_CHAUSIE_HAVE_MCHP_FW),y) +$(call add_intermediate, add_mchp_fw) + $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_CHAUSIE_MCHP_FW_FILE) --fill-upward +else +files_added:: warn_no_mchp +endif # CONFIG_CHAUSIE_HAVE_MCHP_FW + +PHONY+=warn_no_mchp +warn_no_mchp: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without the Microchip EC FW.\n" + printf "Do not flash this image. Your Chausie's power button\n" + printf "will not respond when you press it.\n\n" |