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authorAnand Vaikar <a.vaikar2021@gmail.com>2024-02-06 11:14:17 +0530
committerFelix Held <felix-coreboot@felixheld.de>2024-02-21 19:03:52 +0000
commit7ae2e2840d57060a27859086a076087389e39b77 (patch)
tree2b9ae73963b8f409abe7288d6c7b8232aaa8b450 /src/mainboard/amd/birman_plus/mainboard.c
parent0978973d3f6665e5b6e6af49b048a8d0c5e833d5 (diff)
mb/amd/birman_plus: Add Birman+ board support for Phoenix SOC
1) Initial commit for upstreaming Birmanplus mainboard changes. 2) Add the DXIO descriptors for Birmanplus mainboard. Change-Id: I075dcf0214f8dc8b33b0e429d83d270b2f0952e1 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/mainboard/amd/birman_plus/mainboard.c')
-rw-r--r--src/mainboard/amd/birman_plus/mainboard.c65
1 files changed, 65 insertions, 0 deletions
diff --git a/src/mainboard/amd/birman_plus/mainboard.c b/src/mainboard/amd/birman_plus/mainboard.c
new file mode 100644
index 0000000000..0deba6710f
--- /dev/null
+++ b/src/mainboard/amd/birman_plus/mainboard.c
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/acpi.h>
+#include <amdblocks/amd_pci_util.h>
+#include <commonlib/helpers.h>
+#include <device/device.h>
+#include <types.h>
+#include "gpio.h"
+
+/* TODO: Update for birman */
+
+/* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
+ accessed via I/O ports 0xc00/0xc01. */
+
+/*
+ * This controls the device -> IRQ routing.
+ *
+ * Hardcoded IRQs:
+ * 0: timer < soc/amd/common/acpi/lpc.asl
+ * 1: i8042 - Keyboard
+ * 2: cascade
+ * 8: rtc0 <- soc/amd/common/acpi/lpc.asl
+ * 9: acpi <- soc/amd/common/acpi/lpc.asl
+ */
+static const struct fch_irq_routing fch_irq_map[] = {
+ { PIRQ_A, 12, PIRQ_NC },
+ { PIRQ_B, 14, PIRQ_NC },
+ { PIRQ_C, 15, PIRQ_NC },
+ { PIRQ_D, 12, PIRQ_NC },
+ { PIRQ_E, 14, PIRQ_NC },
+ { PIRQ_F, 15, PIRQ_NC },
+ { PIRQ_G, 12, PIRQ_NC },
+ { PIRQ_H, 14, PIRQ_NC },
+
+ { PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ },
+ { PIRQ_SDIO, PIRQ_NC, PIRQ_NC },
+ { PIRQ_GPIO, 11, 11 },
+ { PIRQ_I2C0, 10, 10 },
+ { PIRQ_I2C1, 7, 7 },
+ { PIRQ_I2C2, 6, 6 },
+ { PIRQ_I2C3, 5, 5 },
+ { PIRQ_UART0, 4, 4 },
+ { PIRQ_UART1, 3, 3 },
+
+ /* The MISC registers are not interrupt numbers */
+ { PIRQ_MISC, 0xfa, 0x00 },
+ { PIRQ_MISC0, 0x91, 0x00 },
+ { PIRQ_HPET_L, 0x00, 0x00 },
+ { PIRQ_HPET_H, 0x00, 0x00 },
+};
+
+const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
+{
+ *length = ARRAY_SIZE(fch_irq_map);
+ return fch_irq_map;
+}
+
+static void mainboard_init(void *chip_info)
+{
+ mainboard_program_gpios();
+}
+
+struct chip_operations mainboard_ops = {
+ .init = mainboard_init,
+};