diff options
| author | Aamir Bohra <aamirbohra@gmail.com> | 2021-04-15 14:56:03 +0530 |
|---|---|---|
| committer | Nick Vaccaro <nvaccaro@google.com> | 2021-08-09 18:06:08 +0000 |
| commit | c29df438c42e162cf385b06ac6df403dbc1841ed (patch) | |
| tree | 1d6af190884ae1ea59cd0e774e4a6c73ce6ce320 /src/mainboard/amd/bilby | |
| parent | 0e5b713d32d09751155746ab2950f2addd184096 (diff) | |
mb/amd/bilby: Set Clk always on for x4 and x8 external PCIe Slot
Keep the clock source for PCIe slots as always on. Also turn off the
unused (0/1/5/6) clock sources. Currently bilby only uses clock sources
2, 3 and 4, out of which clock source 3 and 4 are routed for PCIe
external slot. And clock source 2 is routed for M.2 PCIe slot.
TEST:Verify end devices enumerate on D:F 1.1/1.2 RPs over warm reboot.
Signed-off-by: Aamir Bohra <aamirbohra@gmail.com>
Change-Id: Ida485b06279b0a8659c8d00873c3d6023d1e542f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56826
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/amd/bilby')
| -rw-r--r-- | src/mainboard/amd/bilby/devicetree.cb | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index 2d55a449ae..7073aeeeac 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -137,13 +137,13 @@ chip soc/amd/picasso }" # genral purpose PCIe clock output configuration - register "gpp_clk_config[0]" = "GPP_CLK_REQ" - register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[0]" = "GPP_CLK_OFF" + register "gpp_clk_config[1]" = "GPP_CLK_OFF" register "gpp_clk_config[2]" = "GPP_CLK_REQ" - register "gpp_clk_config[3]" = "GPP_CLK_REQ" - register "gpp_clk_config[4]" = "GPP_CLK_REQ" - register "gpp_clk_config[5]" = "GPP_CLK_REQ" - register "gpp_clk_config[6]" = "GPP_CLK_REQ" + register "gpp_clk_config[3]" = "GPP_CLK_ON" + register "gpp_clk_config[4]" = "GPP_CLK_ON" + register "gpp_clk_config[5]" = "GPP_CLK_OFF" + register "gpp_clk_config[6]" = "GPP_CLK_OFF" register "pspp_policy" = "DXIO_PSPP_BALANCED" |