diff options
| author | Ritul Guru <ritul.bits@gmail.com> | 2021-02-05 23:53:28 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2021-02-17 20:00:41 +0000 |
| commit | 286c2f6d4a72473b919ea580786d5497f7ef2dec (patch) | |
| tree | 1c08513c2ec451aeaff40b16e14417c134ce5394 /src/mainboard/amd/bilby/early_gpio.c | |
| parent | 65819cd3644e96f191de04eae8219cab4bc86fb8 (diff) | |
mainboard/amd/bilby: Add Bilby CRB board
Bilby is the reference board for AMD Raven, Raven2 and Picasso APUs.
Bilby mainboard code is taken from mandolin variant Cereme.
These new files are a renamed copy and subsequent patches will be
applied to create a working bilby implementation.
Change-Id: I426966d782e259a971ec36bac2498bc62b4ce7e2
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Diffstat (limited to 'src/mainboard/amd/bilby/early_gpio.c')
| -rw-r--r-- | src/mainboard/amd/bilby/early_gpio.c | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/src/mainboard/amd/bilby/early_gpio.c b/src/mainboard/amd/bilby/early_gpio.c new file mode 100644 index 0000000000..b6ca995c89 --- /dev/null +++ b/src/mainboard/amd/bilby/early_gpio.c @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/gpio.h> +#include "gpio.h" + +/* GPIO pins used by coreboot should be initialized in bootblock */ + +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* not LLB */ + PAD_GPI(GPIO_12, PULL_UP), + /* not USB_OC1_L */ + PAD_GPI(GPIO_17, PULL_UP), + /* not USB_OC2_L */ + PAD_GPI(GPIO_18, PULL_UP), + /* SDIO eMMC power control */ + PAD_NF(GPIO_22, EMMC_PWR_CTRL, PULL_NONE), + /* PCIe Reset 0 */ + PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), + /* PCIe Reset 1 */ + PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), + /* eSPI CS# */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* PC beep to codec */ + PAD_NF(GPIO_91, SPKR, PULL_NONE), +}; + +void mainboard_program_early_gpios(void) +{ + program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset)); +} |