AMD Bettong: refactor PCI interrupt table

1. Use write_pci_int_table to write registers 0xC00/0xC01.
2. Add GPIO, I2C and UART interrupt according
"BKDG for AMD Family 15h Models 60h-6Fh Processors",
50742 Rev 3.01 - July 17, 2015
3. The interrupt valudes are moved from bettong/mptable.c.
All devices work in Windows 10.

Change-Id: Iad13bc02c84a5dfc7c24356436ac560f593304d7
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/11746
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>

1 files changed, 62 insertions, 0 deletions

diff --git a/src/mainboard/amd/bettong/mainboard.c b/src/mainboard/amd/bettong/mainboard.c
index dc5d4385ba..c31f5b7995 100644
--- a/src/mainboard/amd/bettong/mainboard.c
+++ b/src/mainboard/amd/bettong/mainboard.c
@@ -17,6 +17,65 @@
 #include <device/device.h>
 #include <arch/acpi.h>
 #include <agesawrapper.h>
+#include <southbridge/amd/common/amd_pci_util.h>
+
+/***********************************************************
+ * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
+ * This table is responsible for physically routing the PIC and
+ * IOAPIC IRQs to the different PCI devices on the system.  It
+ * is read and written via registers 0xC00/0xC01 as an
+ * Index/Data pair.  These values are chipset and mainboard
+ * dependent and should be updated accordingly.
+ *
+ * These values are used by the PCI configuration space,
+ * MP Tables.  TODO: Make ACPI use these values too.
+ */
+const u8 mainboard_picr_data[] = {
+	[0x00] = 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,
+	[0x08] = 0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+	[0x10] = 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,
+	[0x18] = 0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
+	[0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x30] = 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,
+	[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x40] = 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x50] = 0x03,0x04,0x05,0x07,0x1F,0x1F,0x1F,0x1F,
+	[0x58] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+	[0x60] = 0x1F,0x1F,0x07,0x1F,0x1F,0x1F,0x1F,0x1F,
+	[0x68] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+	[0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,
+	[0x78] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,
+};
+
+const u8 mainboard_intr_data[] = {
+	[0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
+	[0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
+	[0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x1F,0x1F,0x10,
+	[0x18] = 0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,
+	[0x20] = 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,
+	[0x28] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x30] = 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,
+	[0x38] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x40] = 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x48] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x50] = 0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,
+	[0x58] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x60] = 0x1F,0x1F,0x07,0x00,0x00,0x00,0x00,0x00,
+	[0x68] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+	[0x70] = 0x03,0x0F,0x06,0x0E,0x0A,0x0B,0x1F,0x1F,
+	[0x78] = 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+};
+
+/* PIRQ Setup */
+static void pirq_setup(void)
+{
+	intr_data_ptr = mainboard_intr_data;
+	picr_data_ptr = mainboard_picr_data;
+}
+
+
 
 /*************************************************
  * enable the dedicated function in bettong board.
@@ -27,6 +86,9 @@ static void bettong_enable(device_t dev)
 
 	if (acpi_is_wakeup_s3())
 		agesawrapper_fchs3earlyrestore();
+
+	/* Initialize the PIRQ data structures for consumption */
+	pirq_setup();
 }
 
 struct chip_operations mainboard_ops = {