diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2018-12-21 19:36:35 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-12-29 07:12:56 +0000 |
| commit | 78824238b9613b7927f94db252ed174c86709098 (patch) | |
| tree | 7ac34c944e09d599705cc2354b9514a1a7a30ed0 /src/mainboard/advansus/a785e-i/cmos.layout | |
| parent | 8ae54188531ddadcb252b7c266c475bf1e462b9b (diff) | |
mb/google/sarien: Adjust GPD3 pin termination
Internal pull up need to be enabled for GPD3 as power button pin for
PCH according cannonlake pch EDS vol1 table 17-1. Without that pin will
stay floating and hook up XDP can cause system shutdown as power buttone
event will trigger.
BUG=N/A
TEST=Hook up XDP on sarien platform, able to boot up into OS and stay
at power up state.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ibe21da5f4a0797a3d62b36899f023908b46c25bf
Reviewed-on: https://review.coreboot.org/c/30374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Diffstat (limited to 'src/mainboard/advansus/a785e-i/cmos.layout')
0 files changed, 0 insertions, 0 deletions