diff options
| author | Julia Kittlinger <launchpad.vineyard395@passinbox.com> | 2024-08-18 10:56:29 +0200 |
|---|---|---|
| committer | Felix Singer <service+coreboot-gerrit@felixsinger.de> | 2024-08-18 10:55:38 +0000 |
| commit | 957b6982f637c11db70f2b8d2831941ca5c7a444 (patch) | |
| tree | 43473264e9de096c1391b4d0c855dbb8d8ee72f1 /src/mainboard/acer/g43t-am3/variants/q45t-am/include | |
| parent | 26b1a5f62bb25babfb2a8313db0defd84da681ab (diff) | |
mb/acer/g43t-am3: Add Acer Q45T-AM as a variant
This adds a new board as a variant of the Acer G43T-AM3 with the
following prominent changes:
* Intel Q45 northbridge (GMCH) instead of a G43
* 4 MiB of flash instead of 2 MiB
* Two serial ports (one external, one internal)
* A parallel port connector (internal)
* An FDD connector
* DVI-D instead of HDMI
* No Firewire
The port was done based on logs and info received via private email. It
was only tested on the Acer G43T-AM3 so far, which still builds and works.
Change-Id: Ic2654ca4b198bfea409992be14e89702cf67ea50
Signed-off-by: Julia Kittlinger <launchpad.vineyard395@passinbox.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Diffstat (limited to 'src/mainboard/acer/g43t-am3/variants/q45t-am/include')
| -rw-r--r-- | src/mainboard/acer/g43t-am3/variants/q45t-am/include/acpi/superio.asl | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/mainboard/acer/g43t-am3/variants/q45t-am/include/acpi/superio.asl b/src/mainboard/acer/g43t-am3/variants/q45t-am/include/acpi/superio.asl new file mode 100644 index 0000000000..04fc150acf --- /dev/null +++ b/src/mainboard/acer/g43t-am3/variants/q45t-am/include/acpi/superio.asl @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#undef IT8720F_SHOW_SP1 +#undef IT8720F_SHOW_SP2 +#undef IT8720F_SHOW_EC +#undef IT8720F_SHOW_KBCK +#undef IT8720F_SHOW_KBCM +#undef IT8720F_SHOW_GPIO +#undef IT8720F_SHOW_CIR +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8720F_SHOW_SP1 1 +#define IT8720F_SHOW_SP2 1 +#define IT8720F_SHOW_EC 1 +#define IT8720F_SHOW_KBCK 1 +#define IT8720F_SHOW_KBCM 1 +#define IT8720F_SHOW_GPIO 1 +#define IT8720F_SHOW_CIR 1 +#include <superio/ite/it8720f/acpi/superio.asl> |