mb/acer: Add Acer Aspire VN7-572G

Add initial support for Acer Aspire VN7-572G (Skylake-U).

Also note that there are two similar boards, Aspire VN7-792G and
Aspire VN7-592G; both are Skylake-H. These are not supported (yet).
Do not flash images intended for Aspire VN7-572G on those boards: the
GPIOs and HSIO routing will be different and may risk damage
to the hardware.

Working:
- Payload
  - TianoCore (custom fork of MrChromebox's UefiPayloadPkg; edk2-202102)
- OS
  - Fedora 35 (kernel 5.14.15)
  - Windows 10 20H1 (bugs present: battery paging fixed; abandoning testing)
- Both DIMM slots
- eDP and HDMI display (VBT partially matches vendor's configuration)
  - with FSP GOP
  - with IntelGopDriver (in payload: TianoCore)
  - with libgfxinit
- Audio
  - Speakers and headphone jack
  - Internal microphone
  - HDMI audio
- Devices
  - PCIe and SATA (unable to test M.2 SATA)
    - Discrete graphics, Ethernet and WiFi
  - USB ports (unable to test type-C, touchscreen and fingerprint reader)
    - Includes internal devices (Bluetooth, SD card reader and webcam)
  - TPM
  - Keyboard and touchpad
- Optimus (see CB:28380, CB:40625 and CB:40628)
- ACPI functionality
  - S3 suspend and resume
  - EC support
- Internal flashing with flashrom
- CMOS settings

In progress:
- EC SMM functionality

Not working:
- vboot (breaks boot): See CB:58249

Notes:
- `tpm2_pcrallocate` to enable SHA256 PCR bank

Not implemented:
- WMI

Change-Id: I6340116abfeb2fbd280d143b74d323e4da3566f6
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 16 insertions, 0 deletions

diff --git a/src/mainboard/acer/aspire_vn7_572g/board.fmd b/src/mainboard/acer/aspire_vn7_572g/board.fmd
new file mode 100644
index 0000000000..44d8a0cd13
--- /dev/null
+++ b/src/mainboard/acer/aspire_vn7_572g/board.fmd
@@ -0,0 +1,16 @@
+# NOTE: Use CONSOLE for SMM debugging
+FLASH 8M {
+	SI_ALL 2M {
+		SI_DESC 0x1000
+		SI_ME 0x1ff000
+	}
+	SI_BIOS 6M {
+		EC 0x20000
+		RW_MRC_CACHE 0x10000
+		# SMMSTORE requires 64k alignment
+		SMMSTORE 0x40000
+		CONSOLE 0x20000
+		FMAP 0x200
+		COREBOOT(CBFS) 0x56fe00
+	}
+}