Added support for Aaeon PFM-540I RevB PC104 SBC

The Aaeon PFM-540I RevB SBC is a PC104 SBC using a AMD Geode LX800 CPU.
More infomation about the board available at www.aaeon.com.

Change-Id: Ia8a3caacdc9ff1820a6c0a13a9a7ee758b929dfd
Signed-off-by: Mark Norman <mpnorman@gmail.com>
Reviewed-on: http://review.coreboot.org/30
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 89 insertions, 0 deletions

diff --git a/src/mainboard/aaeon/pfm-540i_revb/romstage.c b/src/mainboard/aaeon/pfm-540i_revb/romstage.c
new file mode 100644
index 0000000000..b638a07427
--- /dev/null
+++ b/src/mainboard/aaeon/pfm-540i_revb/romstage.c
@@ -0,0 +1,89 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2011 Mark Norman <mpnorman@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+/* Based on romstage.c from AMD's DB800 mainboard. */
+
+#include <stdint.h>
+#include <stdlib.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/hlt.h>
+#include <console/console.h>
+#include "cpu/x86/bist.h"
+#include "cpu/x86/msr.h"
+#include <cpu/amd/lxdef.h>
+#include "southbridge/amd/cs5536/cs5536.h"
+#include <spd.h>
+#include "southbridge/amd/cs5536/early_smbus.c"
+#include "southbridge/amd/cs5536/early_setup.c"
+#include "superio/smsc/smscsuperio/early_serial.c"
+
+#define SERIAL_DEV PNP_DEV(0x4e, SMSCSUPERIO_SP1)
+
+static inline int spd_read_byte(unsigned int device, unsigned int address)
+{
+	if (device != DIMM0)
+		return 0xFF;	/* No DIMM1, don't even try. */
+
+	return smbus_read_byte(device, address);
+}
+
+#define ManualConf 0		/* Do automatic strapped PLL config */
+#define PLLMSRhi 0x000005DD	/* Manual settings for the PLL */
+#define PLLMSRlo 0x00DE60EE
+
+#include "northbridge/amd/lx/raminit.h"
+#include "northbridge/amd/lx/pll_reset.c"
+#include "northbridge/amd/lx/raminit.c"
+#include "lib/generic_sdram.c"
+#include "cpu/amd/model_lx/cpureginit.c"
+#include "cpu/amd/model_lx/syspreinit.c"
+#include "cpu/amd/model_lx/msrinit.c"
+
+void main(unsigned long bist)
+{
+	static const struct mem_controller memctrl[] = {
+		{.channel0 = {DIMM0, DIMM1}}
+	};
+
+	SystemPreInit();
+	msr_init();
+
+	cs5536_early_setup();
+
+	/* Note: must do this AFTER the early_setup! It is counting on some
+	 * early MSR setup for CS5536.
+	 */
+	smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
+
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
+	pll_reset(ManualConf);
+
+	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
+
+	sdram_initialize(1, memctrl);
+
+	/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
+}