diff options
author | Mark Norman <mpnorman@gmail.com> | 2011-06-14 22:20:37 +0930 |
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committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-06-29 18:32:59 +0200 |
commit | 0d21cd36b781076409d370935faf6081d970f644 (patch) | |
tree | 48ad28656f837ee2c7cbf63d33b1622f41ab3d2a /src/mainboard/aaeon/pfm-540i_revb/devicetree.cb | |
parent | 811787abd5ec0c944a77ad1dda8817c95948b0c4 (diff) |
Added support for Aaeon PFM-540I RevB PC104 SBC
The Aaeon PFM-540I RevB SBC is a PC104 SBC using a AMD Geode LX800 CPU.
More infomation about the board available at www.aaeon.com.
Change-Id: Ia8a3caacdc9ff1820a6c0a13a9a7ee758b929dfd
Signed-off-by: Mark Norman <mpnorman@gmail.com>
Reviewed-on: http://review.coreboot.org/30
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/aaeon/pfm-540i_revb/devicetree.cb')
-rw-r--r-- | src/mainboard/aaeon/pfm-540i_revb/devicetree.cb | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb b/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb new file mode 100644 index 0000000000..b049160c6d --- /dev/null +++ b/src/mainboard/aaeon/pfm-540i_revb/devicetree.cb @@ -0,0 +1,74 @@ +chip northbridge/amd/lx + device pci_domain 0 on + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + device pci 1.2 on end # AES + chip southbridge/amd/cs5536 + # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK + # SIRQ Mode = Active(Quiet) mode. Save power.... + # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK + register "lpc_serirq_enable" = "0x0000105a" + register "lpc_serirq_polarity" = "0x0000EFA5" + register "lpc_serirq_mode" = "1" + register "enable_gpio_int_route" = "0x0D0C0700" + register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash + register "enable_USBP4_device" = "1" # 0: host, 1:device + register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381) + register "com1_enable" = "0" + register "com1_address" = "0x3E8" + register "com1_irq" = "4" + register "com2_enable" = "0" + register "com2_address" = "0x2E8" + register "com2_irq" = "3" + register "unwanted_vpci[0]" = "0" # End of list has a zero + device pci c.0 on end # ISA Bridge (PC104) + device pci e.0 on end # Ethernet + device pci f.0 on # ISA Bridge + chip superio/smsc/smscsuperio + device pnp 4e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 4e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 4e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 4e.5 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 4e.7 on # Keyboard + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 4e.a off end # Runtime/ACPI + + # superio/smsc/smscsuperio currently only supports the first 2 serial ports. + device pnp 4e.b off # Com3 + io 0x60 = 0x3e8 + irq 0x70 = 10 + end + device pnp 4e.c off # Com4 + io 0x60 = 0x2e8 + irq 0x70 = 11 + end + end + end + device pci f.2 on end # IDE Controller + device pci f.4 on end # OHCI + device pci f.5 on end # EHCI + end + end + # APIC cluster is late CPU init. + device lapic_cluster 0 on + chip cpu/amd/model_lx + device lapic 0 on end + end + end +end + |