- Bump the LinuxBIOS major version

- Rename chip_config chip_operations throughout the tree
- Fix Config.lb on most of the Opteron Ports
- Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
- Add detection of devices that are on the motherboard (i.e. In Config.lb)
- Baby step in getting the resource limit handling correct, Ignore fixed resources
- Only call enable_childrens_resources on devices we know will have children
  For some busses like i2c it is non-sense and we don't want it.
- Set the resource limits for pnp devices resources.
- Improve the resource size detection for pnp devices.
- Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
- Added a header file to hold the prototype of isa_dma_init
- Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
- The code compiles and runs so it is time for me to go to bed.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

3 files changed, 87 insertions, 114 deletions

diff --git a/src/mainboard/Iwill/DK8S2/Config.lb b/src/mainboard/Iwill/DK8S2/Config.lb
index 635de88a70..47400f8559 100644
--- a/src/mainboard/Iwill/DK8S2/Config.lb
+++ b/src/mainboard/Iwill/DK8S2/Config.lb
@@ -242,95 +242,92 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
 dir /pc80
 config chip.h
 
-northbridge amd/amdk8 "mc0"
-	pci 0:18.0
-	pci 0:18.0
-	pci 0:18.0
-	pci 0:18.1
-	pci 0:18.2
-	pci 0:18.3
-	southbridge amd/amd8131 "amd8131" link 0
-		pci 0:0.0
-		pci 0:0.1
-		pci 0:1.0
-		pci 0:1.1
+chip northbridge/amd/amdk8
+	device pci_domain 0 on
+		device pci 18.0 on # LDT 0
+			chip southbridge/amd/amd8131
+				device pci 0.0 on end
+				device pci 0.1 on end
+				device pci 1.0 on end
+				device pci 1.1 on end
+			end
+			chip southbridge/amd/amd8111
+				# this "device pci 0.0" is the parent the next one
+				# PCI bridge
+				device pci 0.0 on
+					device pci 0.0 on end
+					device pci 0.1 on end
+					device pci 0.2 on end
+					device pci 1.0 off end
+				end
+				device pci 1.0 on
+					chip superio/winbond/w83627hf
+						device pnp  2e.0 on      # Floppy
+							 io 0x60 = 0x3f0
+							irq 0x70 = 6
+							drq 0x74 = 2
+						end
+						device pnp  2e.1 off     # Parallel Port
+							 io 0x60 = 0x378
+							irq 0x70 = 7
+						end
+						device pnp  2e.2 on      # Com1
+							 io 0x60 = 0x3f8
+							irq 0x70 = 4
+						end
+						device pnp  2e.3 off     # Com2
+							io 0x60 = 0x2f8
+							irq 0x70 = 3
+						end
+						device pnp  2e.5 on      # Keyboard
+							 io 0x60 = 0x60
+							 io 0x62 = 0x64
+						       irq 0x70 = 1
+							irq 0x72 = 12
+						end
+						device pnp  2e.6 off end # CIR
+						device pnp  2e.7 off end # GAME_MIDI_GIPO1
+						device pnp  2e.8 off end # GPIO2
+						device pnp  2e.9 off end # GPIO3
+						device pnp  2e.a off end # ACPI
+						device pnp  2e.b on      # HW Monitor
+							 io 0x60 = 0x290
+						end
+						register "com1" = "{1}"
+					#	register "com1" = "{1, 0, 0x3f8, 4}"
+					#	register "lpt" = "{1}"
+					end
+				end
+				device pci 1.1 on end
+				device pci 1.2 on end
+				device pci 1.3 on end 
+				device pci 1.5 off end
+				device pci 1.6 off end
+			end
+		end # LDT0
+		device pci 18.0 on end # LDT1
+		device pci 18.0 on end # LDT2
+		device pci 18.1 on end
+		device pci 18.2 on end
+		device pci 18.3 on end
+
+		chip northbridge/amd/amdk8
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.0 on end
+			device pci 19.1 on end
+			device pci 19.2 on end
+			device pci 19.3 on end
+		end
+	end 
+	device apic_cluster 0 on
+		chip cpu/amd/socket_940
+			device apic 0 on end
+		end
+		chip cpu/amd/socket_940
+			device apic 1 on end
+		end
 	end
-	southbridge amd/amd8111 "amd8111" link 0
-		pci 0:0.0
-		pci 0:1.0 on
-		pci 0:1.1 on
-		pci 0:1.2 on
-		pci 0:1.3 on
-		pci 0:1.5 off
-		pci 0:1.6 off
-		pci 1:0.0 on
-		pci 1:0.1 on
-		pci 1:0.2 on
-		pci 1:1.0 off
-
-                superio winbond/w83627hf link 1
-                        pnp 2e.0 on #  Floppy
-                                 io 0x60 = 0x3f0
-                                irq 0x70 = 6
-                                drq 0x74 = 2
-                        pnp 2e.1 off #  Parallel Port
-                                 io 0x60 = 0x378
-                                irq 0x70 = 7
-                        pnp 2e.2 on #  Com1
-                                 io 0x60 = 0x3f8
-                                irq 0x70 = 4
-                        pnp 2e.3 off #  Com2
-                                io 0x60 = 0x2f8
-                                irq 0x70 = 3
-                        pnp 2e.5 on #  Keyboard
-                                 io 0x60 = 0x60
-                                 io 0x62 = 0x64
-                               irq 0x70 = 1
-				irq 0x72 = 12
-                        pnp 2e.6 off #  CIR
-                        pnp 2e.7 off #  GAME_MIDI_GIPO1
-                        pnp 2e.8 off #  GPIO2
-                        pnp 2e.9 off #  GPIO3
-                        pnp 2e.a off #  ACPI
-                        pnp 2e.b on  #  HW Monitor
- 				 io 0x60 = 0x290
-			register "com1" = "{1}"
-		#	register "com1" = "{1, 0, 0x3f8, 4}"
-		#	register "lpt" = "{1}"
-                end
-
-#		superio winbond/w83627hf link 1
-#			pnp 2e.0
-#			pnp 2e.1
-#			pnp 2e.2
-#			pnp 2e.3
-#			pnp 2e.4
-#			pnp 2e.5
-#			pnp 2e.6
-#			pnp 2e.7
-#			pnp 2e.8
-#			pnp 2e.9
-#			pnp 2e.a
-#			register "com1" = "{1, 0, 0x3f8, 4}"
-#			register "lpt" = "{1}"
-#		end
-	end
-end
-
-northbridge amd/amdk8 "mc1"
-	pci 0:19.0
-	pci 0:19.0
-	pci 0:19.0
-	pci 0:19.1
-	pci 0:19.2
-	pci 0:19.3
-end
-
-cpu k8 "cpu0"
-	register "ldt0" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
-end
-
-cpu k8 "cpu1" 
 end
 
 ##
diff --git a/src/mainboard/Iwill/DK8S2/chip.h b/src/mainboard/Iwill/DK8S2/chip.h
index 6c0dd885a0..0e961fd0e7 100644
--- a/src/mainboard/Iwill/DK8S2/chip.h
+++ b/src/mainboard/Iwill/DK8S2/chip.h
@@ -1,4 +1,4 @@
-extern struct chip_control mainboard_Iwill_DK8S2_control;
+extern struct chip_operations mainboard_Iwill_DK8S2_control;
 
 struct mainboard_Iwill_DK8S2_config {
 	int nothing;
diff --git a/src/mainboard/Iwill/DK8S2/mainboard.c b/src/mainboard/Iwill/DK8S2/mainboard.c
index 0f609b3f69..0db6bd043a 100644
--- a/src/mainboard/Iwill/DK8S2/mainboard.c
+++ b/src/mainboard/Iwill/DK8S2/mainboard.c
@@ -9,31 +9,7 @@
 #include "chip.h"
 
 
-unsigned long initial_apicid[CONFIG_MAX_CPUS] =
-{
-	0, 1,
-};
-
-static struct device_operations mainboard_operations = {
-	.read_resources   = root_dev_read_resources,
-	.set_resources    = root_dev_set_resources,
-	.enable_resources = enable_childrens_resources,
-	.init             = 0,
-	.scan_bus         = amdk8_scan_root_bus,
-	.enable           = 0,
-};
-
-static void enumerate(struct chip *chip)
-{
-	struct chip *child;
-	dev_root.ops = &mainboard_operations;
-	chip->dev = &dev_root;
-	chip->bus = 0;
-	for(child = chip->children; child; child = child->next) {
-		child->bus = &dev_root.link[0];
-	}
-}
-struct chip_control mainboard_Iwill_DK8S2_control = {
+struct chip_operations mainboard_Iwill_DK8S2_control = {
 	.enumerate = enumerate, 
 	.name      = "Iwill DK8S2 mainboard ",
 };