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authorBernardo Perez Priego <bernardo.perez.priego@intel.com>2021-06-22 17:59:38 -0700
committerWerner Zeh <werner.zeh@siemens.com>2021-06-28 04:26:53 +0000
commit43fd0402265c0c1381fc3fcf04610ed9f2781f2f (patch)
treed56ea00ec8a9082c26a9f5d0e0dcac349811c7b7 /src/mainboard/51nb
parentfa6d31f9997278714d409512b0f77acbf55b32e2 (diff)
mb/intel/adlrvp_m: Enable TCSS USB ports device path
This provide a more consistent mechanism to enable corresponding USB TCSS port. BUG=b:182960979 TEST=Boot device, Type C port should operate correctly. Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com> Change-Id: Iadc0df2e6e19a5afacbb7db1ae0bc7546dbcdc1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/55772 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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