diff options
| author | Dan Ehrenberg <dehrenberg@chromium.org> | 2015-01-08 10:29:19 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2015-04-17 09:21:07 +0200 |
| commit | a5aac76ac6be23448c164b0bc8047facb7238cdf (patch) | |
| tree | 50bdd770ce2e8b1d257cd6c9cf56fd5cd8635b52 /src/lib | |
| parent | f9b49e8782efb7628984e1f3c3abc1ef7a58b84b (diff) | |
drivers/spi: Pass flash parameters from coreboot to payload
A payload may want to run erase operations on SPI NOR flash without
re-probing the device to get its properties. This patch passes up
three properties of flash to achieve that:
- The size of the flash device
- The sector size, i.e., the granularity of erase
- The command used for erase
The patch sends the parameters through coreboot and then libpayload.
The patch also includes a minor refactoring of the flash erase code.
Parameters are sent up for just one flash device. If multiple SPI
flash devices are probed, the second one will "win" and its
parameters will be sent up to the payload.
TEST=Observed parameters to be passed up to depthcharge through
libpayload and be used to correctly initialize flash and do an erase.
TEST=Winbond and Gigadevices spi flash drivers compile with the changes;
others don't, for seemingly unrelated reasons.
BRANCH=none
BUG=chromium:446377
Change-Id: Ib8be86494b5a3d1cfe1d23d3492e3b5cba5f99c6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 988c8c68bbfcdfa69d497ea5f806567bc80f8126
Original-Change-Id: Ie2b3a7f5b6e016d212f4f9bac3fabd80daf2ce72
Original-Signed-off-by: Dan Ehrenberg <dehrenberg@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/239570
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/9726
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/lib')
| -rw-r--r-- | src/lib/coreboot_table.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index afb6743876..6450b5950f 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -32,6 +32,7 @@ #include <cbfs.h> #include <cbmem.h> #include <bootmem.h> +#include <spi_flash.h> #if CONFIG_CHROMEOS #if CONFIG_HAVE_ACPI_TABLES #include <arch/acpi.h> @@ -468,6 +469,11 @@ unsigned long write_coreboot_table( /* Add RAM config if available */ lb_ram_code(head); +#if IS_ENABLED(CONFIG_SPI_FLASH) + /* Add SPI flash description if available */ + lb_spi_flash(head); +#endif + add_cbmem_pointers(head); /* Add board-specific table entries, if any. */ |