aboutsummaryrefslogtreecommitdiff
path: root/src/lib
diff options
context:
space:
mode:
authorAngel Pons <th3fanbus@gmail.com>2020-01-05 20:21:20 +0100
committerFelix Held <felix-coreboot@felixheld.de>2020-01-10 14:59:46 +0000
commit88521881133e62d8f3298388faa718efabc9107a (patch)
treeb02e605a39741d1416d3ecdd80cdcaa13a774cbc /src/lib
parentd589be3648f3e3c9ef5a0aaac9bfe713c8fef333 (diff)
nb/intel/sandybridge: Add a bunch of MCHBAR defines
While we are at it, also: - Rename related variables to match the register names. - Update some comments to better reflect what some registers are about. - Add various FIXME comments on registers that seem to be used wrongly. With BUILD_TIMELESS=1, this commit does not change the coreboot build of: - Asus P8H61-M PRO with native raminit. - Gigabyte GA-H61MA-D3V with native raminit. - Lenovo Thinkpad X230 with native raminit. - Lenovo Thinkpad X220 with MRC raminit. Change-Id: I5e5fe56eaa90842dbbdd1bfbbcb7709237b4c486 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/lib')
0 files changed, 0 insertions, 0 deletions