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| author | Angel Pons <th3fanbus@gmail.com> | 2020-10-28 19:52:22 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-01-10 15:43:10 +0000 |
| commit | 15e5e514613bbf25ca5cd5cba81bde31b4085d0b (patch) | |
| tree | 264840897f5be0ac2855a22c06af01c2af0e74dd /src/lib/memcpy.c | |
| parent | 4c95f10232b7287ba187b358056b92ed73980cfa (diff) | |
cpu/intel/haswell/haswell.h: Align with Broadwell
Sort MSR definitions, move MCHBAR registers to northbridge and relocate
C-state latency macros into the header.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I3b02f1b1eff522c037e6fc8bb0d831423913da29
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46914
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/lib/memcpy.c')
0 files changed, 0 insertions, 0 deletions