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authorEdwin Beasant <edwin_beasant@virtensys.com>2010-06-10 15:24:57 +0000
committerEdwin Beasant <edwin_beasant@virtensys.com>2010-06-10 15:24:57 +0000
commitf333ba09580c00a6f27e3ee0796431f5df936ecf (patch)
treed9d961b45e248d59bf8e3e582b1619887d1921b9 /src/include
parent1965a237124cc8e988cf760eb7e9a61efb2adabb (diff)
This commit updates the Geode LX GLCP delay control setup from the v2 way to the v3 way.
This resolves problems with terminated DRAM modules. Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com> Acked-by: Roland G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/include')
-rw-r--r--src/include/cpu/amd/lxdef.h9
-rw-r--r--src/include/cpu/x86/msr.h6
2 files changed, 14 insertions, 1 deletions
diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h
index d312c0e6da..16a22ba10f 100644
--- a/src/include/cpu/amd/lxdef.h
+++ b/src/include/cpu/amd/lxdef.h
@@ -623,9 +623,16 @@
#define SMM_OFFSET 0x80400000 /* above 2GB */
#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */
+/* DRAM_TERMINATED affects how the DELAY register is set. */
+#define DRAM_TERMINATED 'T'
+#define DRAM_UNTERMINATED 't'
+/* Bitfield definitions for the DELAY register */
+#define DELAY_UPPER_DISABLE_CLK135 (1 << 23)
+#define DELAY_LOWER_STATUS_MASK 0x7C0
+
#if !defined(__ROMCC__) && !defined(ASSEMBLY)
#if defined(__PRE_RAM__)
-void cpuRegInit(void);
+void cpuRegInit(int debug_clock_disable, u8 dimm0, u8 dimm1, int terminated);
void SystemPreInit(void);
#endif
void cpubug(void);
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index daa7e18422..a201ef42f2 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -23,6 +23,12 @@ typedef struct msr_struct
unsigned hi;
} msr_t;
+typedef struct msrinit_struct
+{
+ unsigned index;
+ msr_t msr;
+} msrinit_t;
+
static inline msr_t rdmsr(unsigned index)
{
msr_t result;