diff options
| author | Sugnan Prabhu S <sugnan.prabhu.s@intel.com> | 2021-08-31 07:11:35 +0530 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2021-09-02 22:54:35 +0000 |
| commit | d1fc832c527699265c7d04517010cc4b0ea6aabd (patch) | |
| tree | 74deb12c6e985c6502b5d038a3f8f3fde0fbee21 /src/include | |
| parent | fcb4f2d77e4d0c09bf8e433d724ef0ea272df815 (diff) | |
wifi: Add support for per-platform antenna gain
Add support for the PPAG ACPI BIOS configuration table as per the
connectivity document:
559910_Intel_Connectivity_Platforms_BIOS_Guidelines_Rev6_4.pdf
BUG=b:193665559
TEST=Generated SAR file with the PPAG related configuration values and
verified that the SSDT has the PPAG ACPI table.
Change-Id: Ie8d25113feeeb4a4242cfd7d72a5091d2d5fb389
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/sar.h | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/src/include/sar.h b/src/include/sar.h index 625fd51648..e8a1b287b5 100644 --- a/src/include/sar.h +++ b/src/include/sar.h @@ -4,9 +4,10 @@ #include <stdint.h> +#define MAX_ANT_GAINS_REVISION 2 #define MAX_DSAR_SET_COUNT 3 #define MAX_GEO_OFFSET_REVISION 3 -#define MAX_PROFILE_COUNT 2 +#define MAX_PROFILE_COUNT 3 #define MAX_SAR_REVISION 2 #define REVISION_SIZE 1 #define SAR_REV0_CHAINS_COUNT 2 @@ -30,6 +31,14 @@ struct sar_profile { uint8_t sar_table[0]; } __packed; +struct gain_profile { + uint8_t revision; + uint8_t mode; + uint8_t chains_count; + uint8_t bands_count; + uint8_t ppag_table[0]; +} __packed; + struct sar_header { char marker[SAR_STR_PREFIX_SIZE]; uint8_t version; @@ -41,6 +50,7 @@ union wifi_sar_limits { struct { struct sar_profile *sar; struct geo_profile *wgds; + struct gain_profile *ppag; }; void *profile[MAX_PROFILE_COUNT]; }; |