diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-06-06 17:07:25 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2022-02-05 07:47:17 +0000 |
| commit | c8d26c01584f6a41a6a5e79924742af5d83454f7 (patch) | |
| tree | 3922862d56046bda280ade16bca79ce0535cc459 /src/include | |
| parent | ceaf959678905f44a54a116f37bd15acab5d4608 (diff) | |
cpu/x86/lapic: Support switching to X2APIC mode
The options X2APIC_ONLY and X2APIC_RUNTIME were already user-visible
choices in menuconfig, but the functionality was not actually provided
except for platforms where FSP presumably enabled X2APIC.
Add the logic and related logging for switching to X2APIC operation.
TEST: qemu-system-x86_64 -M Q35 -accel kvm -bios coreboot.rom -serial
stdio -smp 2
PARALLEL_MP, and either X2APIC_ONLY or X2APIC_RUNTIME, need to be
selected for the build of emulation/qemu-q35.
Change-Id: I19a990ba287d21ccddaa64601923f1c4830e95e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/cpu/x86/lapic.h | 2 | ||||
| -rw-r--r-- | src/include/cpu/x86/msr.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index 537fa97afe..af0793b7b8 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -59,7 +59,7 @@ static __always_inline void x2apic_send_ipi(uint32_t icrlow, uint32_t apicid) wrmsr(X2APIC_MSR_ICR_ADDRESS, icr); } -static inline bool is_x2apic_mode(void) +static __always_inline bool is_x2apic_mode(void) { if (CONFIG(XAPIC_ONLY)) return false; diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index a8d5e2211b..4d1cb68279 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -24,6 +24,7 @@ #define CPUID_VMX (1 << 5) #define CPUID_SMX (1 << 6) #define CPUID_DCA (1 << 18) +#define CPUID_X2APIC (1 << 21) #define CPUID_AES (1 << 25) #define SGX_GLOBAL_ENABLE (1 << 18) #define PLATFORM_INFO_SET_TDP (1 << 29) |