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authorJamie Chen <jamie.chen@intel.com>2019-12-20 19:30:33 +0800
committerEdward O'Callaghan <quasisec@chromium.org>2020-01-08 05:46:06 +0000
commit6bb9aaf93f40c8852bab933c968d5aef8bb68b32 (patch)
tree9ab9b6d449f40421fa828863fe3d87da857d07db /src/include
parent1c9746ceaf683f97b584a78bde1ea13778ec7cdd (diff)
soc/intel/cannonlake: Add Comet Lake H SA 4+2 Device ID
This patch adds CML-H 4+2 SA DID into systemagent.c and report platform. According to doc #605546: CML-H (4+2) R1: 9B64h BUG:none BRANCH:none TEST:build no error Change-Id: I5bac6173a84a11abd2ce17f82854fbb14fb8558b Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/device/pci_ids.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index 8602683a75..6c3c2980d1 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3403,6 +3403,7 @@
#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_10_2 0x9B35
#define PCI_DEVICE_ID_INTEL_CML_S_P0P1_8_2 0x9B43
#define PCI_DEVICE_ID_INTEL_CML_H 0x9B54
+#define PCI_DEVICE_ID_INTEL_CML_H_4_2 0x9B64
#define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44
#define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14
#define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12