diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2019-10-21 22:25:04 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-05 15:05:22 +0000 |
| commit | 6b5bf407deb52a900ef0a8a0b99f853be1eb7e82 (patch) | |
| tree | 283c0d2d098d3439e1558729cbdb35f9721ab6e6 /src/include | |
| parent | 8fc523e3137cfdde970a3c87e22b8bbc586a3f7e (diff) | |
soc/intel/common: Include Tigerlake device IDs
Add Tigerlake specific CPU, System Agent, PCH, IGD device IDs.
BUG=None
BRANCH=None
TEST=Build 'emerge-tglrvp coreboot'
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I19047354718bdf510dffee4659d885f1313a751b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Diffstat (limited to 'src/include')
| -rw-r--r-- | src/include/device/pci_ids.h | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 3cab86bd1c..4d21f5b045 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2767,6 +2767,7 @@ #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_U_LPC 0x0284 #define PCI_DEVICE_ID_INTEL_CMP_BASE_U_LPC 0x0285 #define PCI_DEVICE_ID_INTEL_CMP_SUPER_Y_LPC 0x0286 +#define PCI_DEVICE_ID_INTEL_TGL_ESPI 0xA083 /* Intel PCIE device ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PCIE_RP1 0x9d10 @@ -2903,6 +2904,23 @@ #define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP15 0x34b6 #define PCI_DEVICE_ID_INTEL_ICP_LP_PCIE_RP16 0x34b7 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP1 0xa0b8 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP2 0xa0b9 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP3 0xa0ba +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP4 0xa0bb +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP5 0xa0bc +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP6 0xa0bd +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP7 0xa0be +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP8 0xa0bf +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP9 0xa0b0 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP10 0xa0b1 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP11 0xa0b2 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP12 0xa0b3 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP13 0xa0b4 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP14 0xa0b5 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP15 0xa0b6 +#define PCI_DEVICE_ID_INTEL_TGP_LP_PCIE_RP16 0xa0b7 + #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP1 0xa338 #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP2 0xa339 #define PCI_DEVICE_ID_INTEL_CNP_H_PCIE_RP3 0xa33a @@ -2972,6 +2990,10 @@ #define PCI_DEVICE_ID_INTEL_CMP_SATA 0x02d5 #define PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA 0x02d7 #define PCI_DEVICE_ID_INTEL_CMP_LP_SATA 0x02d3 +#define PCI_DEVICE_ID_INTEL_TGP_LP_SATA 0xa0d3 +#define PCI_DEVICE_ID_INTEL_TGP_SATA 0xa0d5 +#define PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA 0xa0d7 +#define PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA 0x282a /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -2985,6 +3007,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_PMC 0xa321 #define PCI_DEVICE_ID_INTEL_ICP_PMC 0x34a1 #define PCI_DEVICE_ID_INTEL_CMP_PMC 0x02a1 +#define PCI_DEVICE_ID_INTEL_TGP_PMC 0xa0a1 /* Intel I2C device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_I2C0 0x9d60 @@ -3035,6 +3058,14 @@ #define PCI_DEVICE_ID_INTEL_CMP_I2C3 0x02eb #define PCI_DEVICE_ID_INTEL_CMP_I2C4 0x02c5 #define PCI_DEVICE_ID_INTEL_CMP_I2C5 0x02c6 +#define PCI_DEVICE_ID_INTEL_TGP_I2C0 0xa0e8 +#define PCI_DEVICE_ID_INTEL_TGP_I2C1 0xa0e9 +#define PCI_DEVICE_ID_INTEL_TGP_I2C2 0xa0ea +#define PCI_DEVICE_ID_INTEL_TGP_I2C3 0xa0eb +#define PCI_DEVICE_ID_INTEL_TGP_I2C4 0xa0c5 +#define PCI_DEVICE_ID_INTEL_TGP_I2C5 0xa0c6 +#define PCI_DEVICE_ID_INTEL_TGP_I2C6 0xa0d8 +#define PCI_DEVICE_ID_INTEL_TGP_I2C7 0xa0d9 /* Intel UART device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_UART0 0x9d27 @@ -3066,6 +3097,9 @@ #define PCI_DEVICE_ID_INTEL_CMP_UART0 0x02a8 #define PCI_DEVICE_ID_INTEL_CMP_UART1 0x02a9 #define PCI_DEVICE_ID_INTEL_CMP_UART2 0x02c7 +#define PCI_DEVICE_ID_INTEL_TGP_UART0 0xa0a8 +#define PCI_DEVICE_ID_INTEL_TGP_UART1 0xa0a9 +#define PCI_DEVICE_ID_INTEL_TGP_UART2 0xa0c7 /* Intel SPI device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_SPI1 0x9d24 @@ -3096,6 +3130,14 @@ #define PCI_DEVICE_ID_INTEL_CMP_SPI1 0x02ab #define PCI_DEVICE_ID_INTEL_CMP_SPI2 0x02fb #define PCI_DEVICE_ID_INTEL_CMP_HWSEQ_SPI 0x02a4 +#define PCI_DEVICE_ID_INTEL_TGP_SPI0 0xa0a4 +#define PCI_DEVICE_ID_INTEL_TGP_GSPI0 0xa0aa +#define PCI_DEVICE_ID_INTEL_TGP_GSPI1 0xa0ab +#define PCI_DEVICE_ID_INTEL_TGP_GSPI2 0x34fb +#define PCI_DEVICE_ID_INTEL_TGP_GSPI3 0xa0fd +#define PCI_DEVICE_ID_INTEL_TGP_GSPI4 0xa0fe +#define PCI_DEVICE_ID_INTEL_TGP_GSPI5 0xa0de +#define PCI_DEVICE_ID_INTEL_TGP_GSPI6 0xa0df /* Intel IGD device Ids */ #define PCI_DEVICE_ID_INTEL_SKL_GT1F_DT2 0x1902 @@ -3187,6 +3229,10 @@ #define PCI_DEVICE_ID_INTEL_CML_GT1_H_2 0x9B22 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_1 0x9B44 #define PCI_DEVICE_ID_INTEL_CML_GT2_H_2 0x9B42 +#define PCI_DEVICE_ID_INTEL_TGL_GT1 0X9A60 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_UY 0X9A49 +#define PCI_DEVICE_ID_INTEL_TGL_GT2 0XFF20 +#define PCI_DEVICE_ID_INTEL_TGL_GT2_Y 0X9A40 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -3237,6 +3283,8 @@ #define PCI_DEVICE_ID_INTEL_CML_S_10_2 0x9B35 #define PCI_DEVICE_ID_INTEL_CML_H 0x9B54 #define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44 +#define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14 +#define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A12 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 @@ -3247,6 +3295,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SMBUS 0xa323 #define PCI_DEVICE_ID_INTEL_ICP_LP_SMBUS 0x34a3 #define PCI_DEVICE_ID_INTEL_CMP_SMBUS 0x02a3 +#define PCI_DEVICE_ID_INTEL_TGP_LP_SMBUS 0xa0a3 /* Intel XHCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8 @@ -3260,6 +3309,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_XHCI 0xa36d #define PCI_DEVICE_ID_INTEL_ICP_LP_XHCI 0x34ed #define PCI_DEVICE_ID_INTEL_CMP_LP_XHCI 0x02ed +#define PCI_DEVICE_ID_INTEL_TGP_LP_XHCI 0xa0ed /* Intel P2SB device Ids */ #define PCI_DEVICE_ID_INTEL_APL_P2SB 0x5a92 @@ -3273,6 +3323,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_P2SB 0xa320 #define PCI_DEVICE_ID_INTEL_ICL_P2SB 0x34a0 #define PCI_DEVICE_ID_INTEL_CMP_P2SB 0x02a0 +#define PCI_DEVICE_ID_INTEL_TGL_P2SB 0xa0a0 /* Intel SRAM device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SRAM 0x5aec @@ -3281,6 +3332,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_SRAM 0xa36f #define PCI_DEVICE_ID_INTEL_ICL_SRAM 0x34ef #define PCI_DEVICE_ID_INTEL_CMP_SRAM 0x02ef +#define PCI_DEVICE_ID_INTEL_TGL_SRAM 0xa0ef /* Intel AUDIO device Ids */ #define PCI_DEVICE_ID_INTEL_APL_AUDIO 0x5a98 @@ -3295,6 +3347,7 @@ #define PCI_DEVICE_ID_INTEL_ICL_AUDIO 0x34c8 #define PCI_DEVICE_ID_INTEL_CMP_AUDIO 0x02c8 #define PCI_DEVICE_ID_INTEL_BSW_AUDIO 0x2284 +#define PCI_DEVICE_ID_INTEL_TGL_AUDIO 0xa0c8 /* Intel HECI/ME device Ids */ #define PCI_DEVICE_ID_INTEL_APL_CSE0 0x5a9a @@ -3310,6 +3363,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_CSE0 0xa360 #define PCI_DEVICE_ID_INTEL_ICL_CSE0 0x34e0 #define PCI_DEVICE_ID_INTEL_CMP_CSE0 0x02e0 +#define PCI_DEVICE_ID_INTEL_TGL_CSE0 0xa0e0 /* Intel XDCI device Ids */ #define PCI_DEVICE_ID_INTEL_APL_XDCI 0x5aaa @@ -3319,6 +3373,7 @@ #define PCI_DEVICE_ID_INTEL_CNP_H_XDCI 0xa36e #define PCI_DEVICE_ID_INTEL_ICP_LP_XDCI 0x34ee #define PCI_DEVICE_ID_INTEL_CMP_LP_XDCI 0x02ee +#define PCI_DEVICE_ID_INTEL_TGP_LP_XDCI 0xa0ee /* Intel SD device Ids */ #define PCI_DEVICE_ID_INTEL_APL_SD 0x5aca |