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authorSrinidhi N Kaushik <srinidhi.n.kaushik@intel.com>2020-02-07 15:51:09 -0800
committerPatrick Georgi <pgeorgi@google.com>2020-02-17 15:37:23 +0000
commit1d812e893a2c2e0e6ee1eb9dafb9e681139624e7 (patch)
tree1b676e77dd345f1ae632feb65febbbb8363f11c0 /src/include
parent0ae3a14307274b345846d10d948a1f56ef44dcb3 (diff)
soc/tigerlake: Add Device id for Tiger Lake Dual Core
Add device id for Tiger Lake Dual core part. BUG=b:148965583 BRANCH=none TEST="emerge-tglrvp coreboot chromeos-bootimage", flash and boot Change-Id: Ied0cef2fcc8ae6f25949f98f886c4d79f64b54cd Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/device/pci_ids.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index e117ac2237..c6602c44e3 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3445,6 +3445,7 @@
#define PCI_DEVICE_ID_INTEL_CML_H_8_2 0x9B44
#define PCI_DEVICE_ID_INTEL_TGL_ID_U 0x9A14
#define PCI_DEVICE_ID_INTEL_TGL_ID_U_1 0x9A12
+#define PCI_DEVICE_ID_INTEL_TGL_ID_U_2_2 0x9A04
#define PCI_DEVICE_ID_INTEL_TGL_ID_Y 0x9A10
#define PCI_DEVICE_ID_INTEL_JSL_PRE_PROD 0x4e2a
#define PCI_DEVICE_ID_INTEL_JSL_EHL 0x4532