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authorArthur Heymans <arthur@aheymans.xyz>2019-11-19 18:46:44 +0100
committerKyösti Mälkki <kyosti.malkki@gmail.com>2019-11-21 06:41:09 +0000
commitd9802111122d6273c711eccd352d29d7f34ba4e2 (patch)
treec98f9aff4f07069b4fa72f74dcba48cf06514a70 /src/include
parenteb5147027e974ba365aa4706935c7c9582cf7619 (diff)
soc/intel/fsp_baytrail: Drop support
Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I0b0344f1ebed12207a77c985f27893a1353c0925 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36982 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/reg_script.h5
1 files changed, 2 insertions, 3 deletions
diff --git a/src/include/reg_script.h b/src/include/reg_script.h
index c6fdd523ee..1d0c0d68dc 100644
--- a/src/include/reg_script.h
+++ b/src/include/reg_script.h
@@ -369,8 +369,7 @@ struct reg_script_bus_entry {
REG_RES_RXW32(bar_, reg_, 0xffffffff, value_)
-#if CONFIG(SOC_INTEL_BAYTRAIL) || \
-CONFIG(SOC_INTEL_FSP_BAYTRAIL)
+#if CONFIG(SOC_INTEL_BAYTRAIL)
/*
* IO Sideband Function
*/
@@ -394,7 +393,7 @@ CONFIG(SOC_INTEL_FSP_BAYTRAIL)
REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_)
#define REG_IOSF_XOR(unit_, reg_, value_) \
REG_IOSF_RXW(unit_, reg_, 0xffffffff, value_)
-#endif /* CONFIG_SOC_INTEL_BAYTRAIL || CONFIG_SOC_INTEL_FSP_BAYTRAIL*/
+#endif /* CONFIG_SOC_INTEL_BAYTRAIL */
/*
* CPU Model Specific Register