From d9802111122d6273c711eccd352d29d7f34ba4e2 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 Nov 2019 18:46:44 +0100 Subject: soc/intel/fsp_baytrail: Drop support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are now mandatory features, which this platform lacks. Change-Id: I0b0344f1ebed12207a77c985f27893a1353c0925 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36982 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Reviewed-by: David Hendricks --- src/include/reg_script.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/include') diff --git a/src/include/reg_script.h b/src/include/reg_script.h index c6fdd523ee..1d0c0d68dc 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -369,8 +369,7 @@ struct reg_script_bus_entry { REG_RES_RXW32(bar_, reg_, 0xffffffff, value_) -#if CONFIG(SOC_INTEL_BAYTRAIL) || \ -CONFIG(SOC_INTEL_FSP_BAYTRAIL) +#if CONFIG(SOC_INTEL_BAYTRAIL) /* * IO Sideband Function */ @@ -394,7 +393,7 @@ CONFIG(SOC_INTEL_FSP_BAYTRAIL) REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_) #define REG_IOSF_XOR(unit_, reg_, value_) \ REG_IOSF_RXW(unit_, reg_, 0xffffffff, value_) -#endif /* CONFIG_SOC_INTEL_BAYTRAIL || CONFIG_SOC_INTEL_FSP_BAYTRAIL*/ +#endif /* CONFIG_SOC_INTEL_BAYTRAIL */ /* * CPU Model Specific Register -- cgit v1.2.3