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authorMaulik V Vaghela <maulik.v.vaghela@intel.com>2021-01-29 22:42:08 +0530
committerPatrick Georgi <pgeorgi@google.com>2021-04-06 07:51:05 +0000
commitafb143dadbe3d516e7795e6eeb97367aeb7d4c41 (patch)
tree1b398597628fc8077ce5f52943a46a206bba153f /src/include
parentac91fca8a0277686cf03650f13ff9d39a5882f7c (diff)
soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake M
Added new LPC and IGD device IDs for Alderlake M. Also, added entry for CPUID_ALDERLAKE_M_A0 in report_platform.c TEST=Check if platform information print is coming properly in coreboot Change-Id: If33c43da8cbd786261b00742e342f0f01622c607 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50138 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/device/pci_ids.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index a3382df4ef..520d403f3d 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -3037,6 +3037,7 @@
#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_29 0x549d
#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_30 0x549e
#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_31 0x549f
+#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_32 0x5186
#define PCI_DEVICE_ID_INTEL_SPR_ESPI_1 0x1b80
/* Intel PCIE device ids */
@@ -3808,6 +3809,7 @@
#define PCI_DEVICE_ID_INTEL_ADL_GT1_9 0x4619
#define PCI_DEVICE_ID_INTEL_ADL_P_GT2 0x46a0
#define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680
+#define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0
/* Intel Northbridge Ids */
#define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0