From afb143dadbe3d516e7795e6eeb97367aeb7d4c41 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Fri, 29 Jan 2021 22:42:08 +0530 Subject: soc/intel/alderlake: Add LPC and IGD device Ids for Alderlake M Added new LPC and IGD device IDs for Alderlake M. Also, added entry for CPUID_ALDERLAKE_M_A0 in report_platform.c TEST=Check if platform information print is coming properly in coreboot Change-Id: If33c43da8cbd786261b00742e342f0f01622c607 Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/50138 Reviewed-by: Subrata Banik Reviewed-by: Ronak Kanabar Tested-by: build bot (Jenkins) --- src/include/device/pci_ids.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/include') diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index a3382df4ef..520d403f3d 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3037,6 +3037,7 @@ #define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_29 0x549d #define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_30 0x549e #define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_31 0x549f +#define PCI_DEVICE_ID_INTEL_ADP_M_ESPI_32 0x5186 #define PCI_DEVICE_ID_INTEL_SPR_ESPI_1 0x1b80 /* Intel PCIE device ids */ @@ -3808,6 +3809,7 @@ #define PCI_DEVICE_ID_INTEL_ADL_GT1_9 0x4619 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2 0x46a0 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680 +#define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 -- cgit v1.2.3