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authorPatrick Rudolph <siro@das-labor.org>2016-01-26 20:02:14 +0100
committerMartin Roth <martinroth@google.com>2016-03-02 21:46:49 +0100
commit9f3f9154c9f3dd1e3cfbd2703b681c3e9ddf4dc7 (patch)
treec473e23fc7dc436629f0ca444ccf113173f632e4 /src/include
parent2bdeb7f843c707023ea2bd39e314f8eec51c7add (diff)
nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk
Instead of hardcoding the maximum supported DDR frequency to 800Mhz (DDR3-1600), read the fuse bits that encode this information. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/13487 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/include')
-rw-r--r--src/include/device/dram/ddr3.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index 0520ead4b7..89907ae82a 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -33,8 +33,10 @@
* These values are in 1/256 ns units.
* @{
*/
+#define TCK_1333MHZ 192
+#define TCK_1200MHZ 212
#define TCK_1066MHZ 240
-#define TCK_933MHZ 275
+#define TCK_933MHZ 275
#define TCK_800MHZ 320
#define TCK_666MHZ 384
#define TCK_533MHZ 480