From 9f3f9154c9f3dd1e3cfbd2703b681c3e9ddf4dc7 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Tue, 26 Jan 2016 20:02:14 +0100 Subject: nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk Instead of hardcoding the maximum supported DDR frequency to 800Mhz (DDR3-1600), read the fuse bits that encode this information. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/13487 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/include/device/dram/ddr3.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) (limited to 'src/include') diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 0520ead4b7..89907ae82a 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -33,8 +33,10 @@ * These values are in 1/256 ns units. * @{ */ +#define TCK_1333MHZ 192 +#define TCK_1200MHZ 212 #define TCK_1066MHZ 240 -#define TCK_933MHZ 275 +#define TCK_933MHZ 275 #define TCK_800MHZ 320 #define TCK_666MHZ 384 #define TCK_533MHZ 480 -- cgit v1.2.3