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authorJonathon Hall <jonathon.hall@puri.sm>2023-07-21 13:33:59 -0400
committerFelix Held <felix-coreboot@felixheld.de>2023-09-27 13:37:18 +0000
commit397c15026ecd449b81cbc2beb714175ee911e3e7 (patch)
tree9c224e0cbec68dc5a515914cfeb7e099ab541d35 /src/include/sys
parentad28240e23a6036fa11f36414680da628bc59cc8 (diff)
soc/intel/jasperlake: Set GPE_STS and GPE_EN register bases
Jasper Lake was missing these bases, so attempting to enable an SCI would poke unrelated registers starting from offset 0. Set them so GPEs can be enabled. GPE is used on the Librem 11 for the keyboard dock connector, its sense signal on GPP_D4 raises a GPE which is used to indicate tablet/laptop mode to the OS. The register offsets are documented in the datasheet volume 2 (Intel document 634545), all groups' GPE_STS/GPE_EN start at the same offsets. Change-Id: Ib6b9b9a79e9cc4467e609eaf591ec4e87b78d617 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78097 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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