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authorMaulik V Vaghela <maulik.v.vaghela@intel.com>2021-04-12 22:35:17 +0530
committerPatrick Georgi <pgeorgi@google.com>2021-05-07 09:32:26 +0000
commitce6fdd458b3b93f36a4589584dc13c317c0aa976 (patch)
treee2d9717c1639c6ad0a31badee0d3f1ef65945f19 /src/include/spd_bin.h
parent179f32ff51de908f015295e3d9a750190012eb40 (diff)
mb/intel/adlrvp: Program CPU PCIE RP GPIOs in early GPIO
We need to configure CPU PCIE root port related gpios in early boot block stage for CPU root ports to work. Since we're removing this programming from FSP, coreboot needs to take care of programming this GPIOs. Also we need to enable virtual wire messaging for native gpios for CPU PCIE root ports. Change-Id: Ieda6b6c31ce5bd5e84e4efe544bfc659283ce6f1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52270 Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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