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authorFelix Held <felix-coreboot@felixheld.de>2022-02-03 15:15:37 +0100
committerFelix Held <felix-coreboot@felixheld.de>2022-02-04 15:23:13 +0000
commit8e4742d76de730a29fb9c5d150fb1c9a03c52423 (patch)
tree0572d5598e6c889298abac01e8e004ecd7a04bfa /src/include/sdram_mode.h
parent6151ff3eae6503e1b14fd0898b689f295ddd48f8 (diff)
soc/amd/sabrina/Kconfig: remove TODO from SOC_AMD_COMMON_BLOCK_I2C
Sabrina uses an identical I2C controller as Picasso and Cezanne. Also both the type and version read-only register of the I2C controller contain identical values. The dma_cr, dma_tdlr, dma_rdlr and clr_restart_det registers that are defined in the dw_i2c_regs struct in the common Designware I2C code aren't defined in the PPRs of Picasso, Cezanne and Sabrina, but since common DW I2C code doesn't access those, this is no problem. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I90732aa98518010686f73f80bee229b13e9bc89c Reviewed-on: https://review.coreboot.org/c/coreboot/+/61592 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
Diffstat (limited to 'src/include/sdram_mode.h')
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