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| author | Furquan Shaikh <furquan@chromium.org> | 2017-03-31 13:49:31 -0700 |
|---|---|---|
| committer | Furquan Shaikh <furquan@google.com> | 2017-04-05 20:26:03 +0200 |
| commit | 3255839be15bcccde652891354e91965733f8a86 (patch) | |
| tree | f5226b0806f8196bd944c02dcd3849ddcf9ffacd /src/include/sdram_mode.h | |
| parent | 580e0c584f1ba0f5196c2a3880b55592909d9df4 (diff) | |
soc/intel/skylake: Add tsc_freq.c to verstage
This is required to provide tsc freq required by timer library.
BUG=b:35583330
TEST=Verified that delay(5) in verstage adds a delay of 5 seconds.
Change-Id: I03edebe394522516b46125fae1a17e9a06fd5f45
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/19094
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Diffstat (limited to 'src/include/sdram_mode.h')
0 files changed, 0 insertions, 0 deletions