diff options
| author | Yu-Ping Wu <yupingso@chromium.org> | 2024-07-18 14:41:49 +0800 |
|---|---|---|
| committer | Yu-Ping Wu <yupingso@google.com> | 2024-07-23 07:54:39 +0000 |
| commit | d8bed2d001e8882850643230a45a7dc362e8e368 (patch) | |
| tree | bace8db529bfb7c0d98fce829a37b6aaeb4fbfc9 /src/include/pc80 | |
| parent | 9b2d995bdbef8fd5df5d04ed80f7fb96382e968a (diff) | |
drivers/pc80/rtc/mc146818rtc: Add assertion of bank selection for AMD
As described in CB:83495, in AMD platforms, the bit 4 of CMOS Register A
is bank selection. Since the MC146818 driver accesses VBNV via Bank 0,
the value set in cmos_init() must not contain that bit.
To prevent RTC_FREQ_SELECT_DEFAULT from being incorrectly modified, add
an static assertion about the bank selection for AMD. Note that the
kernel driver also ensures RTC_AMD_BANK_SELECT isn't set for AMD [1].
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/rtc/rtc-mc146818-lib.c?id=3ae8fd4157
BUG=b:346716300
TEST=none
BRANCH=skyrim
Change-Id: I6122201914c40604f86dcca6025b55c595ef609e
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/include/pc80')
| -rw-r--r-- | src/include/pc80/mc146818rtc.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h index 78184214a3..701cc73af8 100644 --- a/src/include/pc80/mc146818rtc.h +++ b/src/include/pc80/mc146818rtc.h @@ -33,6 +33,8 @@ # define RTC_REF_CLCK_4MHZ 0x00 # define RTC_REF_CLCK_1MHZ 0x10 # define RTC_REF_CLCK_32KHZ 0x20 + /* In AMD BKDG, bit 4 is DV0 bank selection. Bits 5 and 6 are reserved. */ +# define RTC_AMD_BANK_SELECT 0x10 /* 2 values for divider stage reset, others for "testing purposes only" */ # define RTC_DIV_RESET1 0x60 # define RTC_DIV_RESET2 0x70 |