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authorSubrata Banik <subrata.banik@intel.com>2019-11-05 18:30:05 +0530
committerSubrata Banik <subrata.banik@intel.com>2019-11-06 04:53:58 +0000
commitfb2a9d5ed86d9d5e5d7a8b20e71df0deba3bc5c0 (patch)
tree8571f80e3f0f6f4bf5387d248597ddb5711188ad /src/include/edid.h
parent6a657c26462f9c5896e504cd4027e58bc6db7d86 (diff)
soc/intel/icelake: Set FSP_TEMP_RAM_STACK unconditionally
Icelake default selects PLATFORM_USES_FSP2_1 which means stack will be shared between FSP and coreboot (CONFIG_FSP_USES_CB_STACK) hence no need to have any other guard to assign FSP_TEMP_RAM_SIZE. Change-Id: Idbe393f7a63ad10f1ad3c9e7248593cf8eb115d9 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36628 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/edid.h')
0 files changed, 0 insertions, 0 deletions