diff options
| author | Saurabh Mishra <mishra.saurabh@intel.com> | 2024-04-12 20:46:46 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-05-14 13:11:04 +0000 |
| commit | 1057865a89568f887f353b020a20d54374acdbe8 (patch) | |
| tree | 9d9cfd26deb6ced79bdfa445ff6a2a233e3538af /src/include/device | |
| parent | 47e7240ffc6a8f479bedc065376fb59cd040c7c7 (diff) | |
soc/intel: Add Panther Lake PCIE device IDs
Add Panther Lake specific CPU and PCIE device IDs
Reference:
Panther Lake External Design Specification Volume 0.51 (815002)
BUG=b:329787286
TEST=verified on Panther Lake Simics Platform.
Change-Id: I82f47b6077e28a01f34c59b7e7697323b3d5f990
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81849
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/pci_ids.h | 66 |
1 files changed, 66 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index e349d2790d..0d1119d71b 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2185,6 +2185,7 @@ #define PCI_DID_INTEL_ADL_N_ISHB 0x54fc #define PCI_DID_INTEL_ADL_P_ISHB 0x51fc #define PCI_DID_INTEL_LNL_ISHB 0xa845 +#define PCI_DID_INTEL_PTL_ISHB 0xe445 /* Intel 82371FB (PIIX) */ #define PCI_DID_INTEL_82371FB_ISA 0x122e @@ -3166,6 +3167,14 @@ #define PCI_DID_INTEL_LNL_ESPI_5 0xa805 #define PCI_DID_INTEL_LNL_ESPI_6 0xa806 #define PCI_DID_INTEL_LNL_ESPI_7 0xa807 +#define PCI_DID_INTEL_PTL_ESPI_0 0xe400 +#define PCI_DID_INTEL_PTL_ESPI_1 0xe401 +#define PCI_DID_INTEL_PTL_ESPI_2 0xe402 +#define PCI_DID_INTEL_PTL_ESPI_3 0xe403 +#define PCI_DID_INTEL_PTL_ESPI_4 0xe404 +#define PCI_DID_INTEL_PTL_ESPI_5 0xe405 +#define PCI_DID_INTEL_PTL_ESPI_6 0xe406 +#define PCI_DID_INTEL_PTL_ESPI_7 0xe407 /* Intel PCIE device ids */ #define PCI_DID_INTEL_LPT_H_PCIE_RP1 0x8c10 @@ -3528,6 +3537,14 @@ #define PCI_DID_INTEL_LNL_PCIE_RP6 0xa83d #define PCI_DID_INTEL_LNL_PCIE_RP7 0xa83e #define PCI_DID_INTEL_LNL_PCIE_RP8 0xa83f +#define PCI_DID_INTEL_PTL_PCIE_RP1 0xe438 +#define PCI_DID_INTEL_PTL_PCIE_RP2 0xe439 +#define PCI_DID_INTEL_PTL_PCIE_RP3 0xe43a +#define PCI_DID_INTEL_PTL_PCIE_RP4 0xe43b +#define PCI_DID_INTEL_PTL_PCIE_RP5 0xe43c +#define PCI_DID_INTEL_PTL_PCIE_RP6 0xe43d +#define PCI_DID_INTEL_PTL_PCIE_RP7 0xe43e +#define PCI_DID_INTEL_PTL_PCIE_RP8 0xe43f #define PCI_DID_INTEL_RPP_S_PCIE_RP1 0x7a38 #define PCI_DID_INTEL_RPP_S_PCIE_RP2 0x7a39 @@ -3672,6 +3689,7 @@ #define PCI_DID_INTEL_RPP_P_PMC 0x51a1 #define PCI_DID_INTEL_RPP_S_PMC 0x7a21 #define PCI_DID_INTEL_LNL_PMC 0xa821 +#define PCI_DID_INTEL_PTL_PMC 0xe421 /* Intel I2C device Ids */ #define PCI_DID_INTEL_LPT_LP_I2C0 0x9c61 @@ -3803,6 +3821,13 @@ #define PCI_DID_INTEL_LNL_I2C4 0xa850 #define PCI_DID_INTEL_LNL_I2C5 0xa851 +#define PCI_DID_INTEL_PTL_I2C0 0xe478 +#define PCI_DID_INTEL_PTL_I2C1 0xe479 +#define PCI_DID_INTEL_PTL_I2C2 0xe47a +#define PCI_DID_INTEL_PTL_I2C3 0xe47b +#define PCI_DID_INTEL_PTL_I2C4 0xe450 +#define PCI_DID_INTEL_PTL_I2C5 0xe451 + /* Intel UART device Ids */ #define PCI_DID_INTEL_LPT_LP_UART0 0x9c63 #define PCI_DID_INTEL_LPT_LP_UART1 0x9c64 @@ -3886,6 +3911,10 @@ #define PCI_DID_INTEL_LNL_UART1 0xa826 #define PCI_DID_INTEL_LNL_UART2 0xa852 +#define PCI_DID_INTEL_PTL_UART0 0xe425 +#define PCI_DID_INTEL_PTL_UART1 0xe426 +#define PCI_DID_INTEL_PTL_UART2 0xe452 + /* Intel SPI device Ids */ #define PCI_DID_INTEL_LPT_LP_GSPI0 0x9c65 #define PCI_DID_INTEL_LPT_LP_GSPI1 0x9c66 @@ -3985,6 +4014,11 @@ #define PCI_DID_INTEL_LNL_GSPI1 0xa830 #define PCI_DID_INTEL_LNL_GSPI2 0xa846 +#define PCI_DID_INTEL_PTL_HWSEQ_SPI 0xe423 +#define PCI_DID_INTEL_PTL_SPI0 0xe427 +#define PCI_DID_INTEL_PTL_SPI1 0xe430 +#define PCI_DID_INTEL_PTL_SPI2 0xe446 + /* Intel IGD device Ids */ #define PCI_DID_INTEL_SKL_GT1F_DT2 0x1902 #define PCI_DID_INTEL_SKL_GT1_SULTM 0x1906 @@ -4150,6 +4184,7 @@ #define PCI_DID_INTEL_LNL_M_GT2 0x64a0 #define PCI_DID_INTEL_TWL_GT1_1 0x46D3 #define PCI_DID_INTEL_TWL_GT1_2 0x46D4 +#define PCI_DID_INTEL_PTL_GT2 0x64a0 /* Intel Northbridge Ids */ #define PCI_DID_INTEL_APL_NB 0x5af0 @@ -4293,6 +4328,7 @@ #define PCI_DID_INTEL_RPL_P_ID_8 0xa716 #define PCI_DID_INTEL_LNL_M_ID 0x6400 #define PCI_DID_INTEL_LNL_M_ID_1 0x6410 +#define PCI_DID_INTEL_PTL_ID 0xb001 /* Intel SMBUS device Ids */ #define PCI_DID_INTEL_LPT_H_SMBUS 0x8c22 @@ -4322,6 +4358,7 @@ #define PCI_DID_INTEL_RPP_P_SMBUS 0x51a3 #define PCI_DID_INTEL_RPP_S_SMBUS 0x7a23 #define PCI_DID_INTEL_LNL_SMBUS 0xa822 +#define PCI_DID_INTEL_PTL_SMBUS 0xe422 /* Intel EHCI device IDs */ #define PCI_DID_INTEL_LPT_H_EHCI_1 0x8c26 @@ -4364,6 +4401,8 @@ #define PCI_DID_INTEL_RPP_S_XHCI 0x7a60 #define PCI_DID_INTEL_LNL_XHCI 0xa87d #define PCI_DID_INTEL_LNL_TCSS_XHCI 0xa831 +#define PCI_DID_INTEL_PTL_XHCI 0xe47d +#define PCI_DID_INTEL_PTL_TCSS_XHCI 0xe431 /* Intel P2SB device Ids */ #define PCI_DID_INTEL_APL_P2SB 0x5a92 @@ -4392,6 +4431,8 @@ #define PCI_DID_INTEL_RPP_S_P2SB 0x7a20 #define PCI_DID_INTEL_LNL_P2SB 0xa820 #define PCI_DID_INTEL_LNL_P2SB2 0xa84c +#define PCI_DID_INTEL_PTL_P2SB 0xe420 +#define PCI_DID_INTEL_PTL_P2SB2 0xe44c /* Intel SRAM device Ids */ #define PCI_DID_INTEL_APL_SRAM 0x5aec @@ -4407,6 +4448,7 @@ #define PCI_DID_INTEL_MTL_IOE_M_SRAM 0x7ebf #define PCI_DID_INTEL_MTL_IOE_P_SRAM 0x7ecf #define PCI_DID_INTEL_LNL_SRAM 0xa87f +#define PCI_DID_INTEL_PTL_SRAM 0xe47f /* Intel AUDIO device Ids */ #define PCI_DID_INTEL_LPT_H_AUDIO 0x8c20 @@ -4473,6 +4515,15 @@ #define PCI_DID_INTEL_LNL_AUDIO_7 0xa82e #define PCI_DID_INTEL_LNL_AUDIO_8 0xa82f +#define PCI_DID_INTEL_PTL_AUDIO_1 0xe428 +#define PCI_DID_INTEL_PTL_AUDIO_2 0xe429 +#define PCI_DID_INTEL_PTL_AUDIO_3 0xe42a +#define PCI_DID_INTEL_PTL_AUDIO_4 0xe42b +#define PCI_DID_INTEL_PTL_AUDIO_5 0xe42c +#define PCI_DID_INTEL_PTL_AUDIO_6 0xe42d +#define PCI_DID_INTEL_PTL_AUDIO_7 0xe42e +#define PCI_DID_INTEL_PTL_AUDIO_8 0xe42f + /* Intel HECI/ME device Ids */ #define PCI_DID_INTEL_LPT_H_MEI 0x8c3a #define PCI_DID_INTEL_LPT_H_MEI_9 0x8cba @@ -4518,6 +4569,10 @@ #define PCI_DID_INTEL_RPP_S_CSE3 0x7a6d #define PCI_DID_INTEL_MTL_CSE0 0x7e70 #define PCI_DID_INTEL_LNL_CSE0 0xa870 +#define PCI_DID_INTEL_PTL_CSE0 0xe470 +#define PCI_DID_INTEL_PTL_CSE1 0xe471 +#define PCI_DID_INTEL_PTL_CSE2 0xe474 +#define PCI_DID_INTEL_PTL_CSE3 0xe475 /* Intel XDCI device Ids */ #define PCI_DID_INTEL_APL_XDCI 0x5aaa @@ -4541,6 +4596,7 @@ #define PCI_DID_INTEL_MTL_XDCI 0x7e7e #define PCI_DID_INTEL_MTL_M_TCSS_XDCI 0x7eb1 #define PCI_DID_INTEL_MTL_P_TCSS_XDCI 0x7ec1 +#define PCI_DID_INTEL_PTL_TCSS_XDCI 0xe432 /* Intel SD device Ids */ #define PCI_DID_INTEL_LPT_LP_SD 0x9c35 @@ -4562,6 +4618,7 @@ /* Intel UFS device Ids */ #define PCI_DID_INTEL_LNL_UFS 0xa847 +#define PCI_DID_INTEL_PTL_UFS 0xe447 /* Intel Thunderbolt device Ids */ #define PCI_DID_INTEL_TGL_TBT_RP0 0x9a23 @@ -4602,6 +4659,8 @@ #define PCI_DID_INTEL_LNL_TBT_RP3 0xa837 #define PCI_DID_INTEL_LNL_TBT_DMA0 0xa833 #define PCI_DID_INTEL_LNL_TBT_DMA1 0xa834 +#define PCI_DID_INTEL_PTL_TBT_DMA0 0xe433 +#define PCI_DID_INTEL_PTL_TBT_DMA1 0xe434 /* Intel WIFI Ids */ #define PCI_DID_1000_SERIES_WIFI 0x0084 @@ -4634,6 +4693,7 @@ #define PCI_DID_TP_6SERIES_WIFI 0x2725 #define PCI_DID_MP_7SERIES_WIFI 0x272b +/* Intel IPU device IDs */ #define PCI_DID_INTEL_TGL_IPU 0x9a19 #define PCI_DID_INTEL_TGL_H_IPU 0x9a39 #define PCI_DID_INTEL_JSL_IPU 0x4e19 @@ -4642,6 +4702,7 @@ #define PCI_DID_INTEL_MTL_IPU 0x7d19 #define PCI_DID_INTEL_RPL_IPU 0xa75d #define PCI_DID_INTEL_LNL_IPU 0x645d +#define PCI_DID_INTEL_PTL_IPU 0xb05d /* Intel Dynamic Tuning Technology Device */ #define PCI_DID_INTEL_CML_DTT 0x1903 @@ -4701,6 +4762,11 @@ #define PCI_DID_INTEL_LNL_CNVI_WIFI_2 0xa842 #define PCI_DID_INTEL_LNL_CNVI_WIFI_3 0xa843 #define PCI_DID_INTEL_LNL_CNVI_BT 0xa876 +#define PCI_DID_INTEL_PTL_CNVI_WIFI_0 0xe440 +#define PCI_DID_INTEL_PTL_CNVI_WIFI_1 0xe441 +#define PCI_DID_INTEL_PTL_CNVI_WIFI_2 0xe442 +#define PCI_DID_INTEL_PTL_CNVI_WIFI_3 0xe443 +#define PCI_DID_INTEL_PTL_CNVI_BT 0xe476 /* Platform Security Engine */ #define PCI_DID_INTEL_LNL_PSE0 0xa862 |