diff options
| author | Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com> | 2023-02-01 17:26:20 -0800 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2023-03-29 13:15:48 +0000 |
| commit | 0a71e09cf9f6b971f3707644fbc7f2b6c396555b (patch) | |
| tree | dbf221a006969735519f0cfefcf052bfbeb6f016 /src/include/device | |
| parent | f5f756d50743e7a23ab99d779bba98b5fec363cf (diff) | |
soc/intel/common: Add Intel Trace Hub driver
From Meteor Lake onwards Intel FSP will generate the Trace Hub related
HOB if the Trace Hub is configured to save data in DRAM. This memory
region is used by Trace Hub to store the traces for debugging purpose.
This driver locates the HOB and marks the memory region reserved so
that OS does not use it.
Intel Trace Hub developer manual can be found via document #671536 on
Intel's website.
Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Diffstat (limited to 'src/include/device')
| -rw-r--r-- | src/include/device/pci_ids.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index d277389cf9..0245086045 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4496,6 +4496,9 @@ #define PCI_DID_INTEL_MTL_CRASHLOG_SRAM 0x7d0d #define PCI_DID_INTEL_RPL_CPU_CRASHLOG_SRAM 0xa77d +/* Intel Trace Hub */ +#define PCI_DID_INTEL_MTL_TRACEHUB 0x7e24 + /* Intel Ethernet Controller device Ids */ #define PCI_DID_INTEL_EHL_GBE_HOST 0x4B32 #define PCI_DID_INTEL_EHL_GBE_PSE_0 0x4BA0 |