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authorMichał Żygowski <michal.zygowski@3mdeb.com>2023-06-30 14:13:58 +0200
committerFelix Held <felix-coreboot@felixheld.de>2023-07-12 13:56:32 +0000
commit8dc16a9ce2ad7ca55cde4ecc6fdacded471d5e8f (patch)
tree45a9dc76dbd933d0d02ec07177355977f9a0dd2d /src/include/device
parent1aa5caf2acc1821f109101308042969a763d4c20 (diff)
soc/intel: Replace number in RPL-S ESPI PCI IDs by chipset name
Change-Id: I68416e1633c3d67070790a9db2cd9a13a8981042 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/include/device')
-rw-r--r--src/include/device/pci_ids.h6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h
index fca9b0dd1f..b311991683 100644
--- a/src/include/device/pci_ids.h
+++ b/src/include/device/pci_ids.h
@@ -2980,9 +2980,9 @@
#define PCI_DID_INTEL_RPP_S_ESPI_1 0x7a01
#define PCI_DID_INTEL_RPP_S_ESPI_2 0x7a02
#define PCI_DID_INTEL_RPP_S_ESPI_3 0x7a03
-#define PCI_DID_INTEL_RPP_S_ESPI_4 0x7a04
-#define PCI_DID_INTEL_RPP_S_ESPI_5 0x7a05
-#define PCI_DID_INTEL_RPP_S_ESPI_6 0x7a06
+#define PCI_DID_INTEL_RPP_S_ESPI_Z790 0x7a04
+#define PCI_DID_INTEL_RPP_S_ESPI_H770 0x7a05
+#define PCI_DID_INTEL_RPP_S_ESPI_B760 0x7a06
#define PCI_DID_INTEL_RPP_S_ESPI_7 0x7a07
#define PCI_DID_INTEL_RPP_S_ESPI_8 0x7a08
#define PCI_DID_INTEL_RPP_S_ESPI_9 0x7a09