From 8dc16a9ce2ad7ca55cde4ecc6fdacded471d5e8f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Fri, 30 Jun 2023 14:13:58 +0200 Subject: soc/intel: Replace number in RPL-S ESPI PCI IDs by chipset name MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I68416e1633c3d67070790a9db2cd9a13a8981042 Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/76192 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai --- src/include/device/pci_ids.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/include/device') diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index fca9b0dd1f..b311991683 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2980,9 +2980,9 @@ #define PCI_DID_INTEL_RPP_S_ESPI_1 0x7a01 #define PCI_DID_INTEL_RPP_S_ESPI_2 0x7a02 #define PCI_DID_INTEL_RPP_S_ESPI_3 0x7a03 -#define PCI_DID_INTEL_RPP_S_ESPI_4 0x7a04 -#define PCI_DID_INTEL_RPP_S_ESPI_5 0x7a05 -#define PCI_DID_INTEL_RPP_S_ESPI_6 0x7a06 +#define PCI_DID_INTEL_RPP_S_ESPI_Z790 0x7a04 +#define PCI_DID_INTEL_RPP_S_ESPI_H770 0x7a05 +#define PCI_DID_INTEL_RPP_S_ESPI_B760 0x7a06 #define PCI_DID_INTEL_RPP_S_ESPI_7 0x7a07 #define PCI_DID_INTEL_RPP_S_ESPI_8 0x7a08 #define PCI_DID_INTEL_RPP_S_ESPI_9 0x7a09 -- cgit v1.2.3