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authorElyes Haouas <ehaouas@noos.fr>2022-12-28 12:33:58 +0100
committerElyes Haouas <ehaouas@noos.fr>2023-01-04 12:39:32 +0000
commitf82e68c900151efae572e3bc19690e978b82ca1b (patch)
treefb3709fdb6601c2417baac81219d71fe999c433f /src/include/device/dram
parentaf6cd3f0b44a39bb6387c8218e5872afb74fcc3f (diff)
spd.h: Move enum ddr3_module_type to ddr3.h
Move specific enum ddr3_module_type to <device/dram/ddr3.h>. Change-Id: I8fd7892dda26158a5bdd6cd4972c7859a252153e Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71547 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/include/device/dram')
-rw-r--r--src/include/device/dram/ddr3.h5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h
index b109a15a61..8886e64ac8 100644
--- a/src/include/device/dram/ddr3.h
+++ b/src/include/device/dram/ddr3.h
@@ -32,10 +32,7 @@
#define SPD_DIMM_PART_LEN 18
/** @} */
-/*
- * Module type (byte 3, bits 3:0) of SPD
- * This definition is specific to DDR3. DDR2 SPDs have a different structure.
- */
+/* Byte 3 [3:0]: DDR3 Module type information */
enum spd_dimm_type_ddr3 {
SPD_DDR3_DIMM_TYPE_UNDEFINED = 0x00,
SPD_DDR3_DIMM_TYPE_RDIMM = 0x01,